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Message-ID: <78f1adee5c6e0c3547c116d0e78fe5b70f9c15e1.camel@mailoo.org>
Subject: Re: [PATCHv2] iommu/arm-smmu-qcom: Add debug support for TLB sync
 timeouts
From:   Vincent Knecht <vincent.knecht@mailoo.org>
To:     Sai Prakash Ranjan <quic_saipraka@quicinc.com>,
        Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Joerg Roedel <joro@8bytes.org>
Cc:     iommu@lists.linux-foundation.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, quic_guptap@quicinc.com,
        Rob Clark <robdclark@chromium.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>
Date:   Wed, 08 Jun 2022 23:22:58 +0200
In-Reply-To: <20220526041403.9984-1-quic_saipraka@quicinc.com>
References: <20220526041403.9984-1-quic_saipraka@quicinc.com>
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Le jeudi 26 mai 2022 =C3=A0 09:44 +0530, Sai Prakash Ranjan a =C3=A9crit=C2=
=A0:
> TLB sync timeouts can be due to various reasons such as TBU power down
> or pending TCU/TBU invalidation/sync and so on. Debugging these often
> require dumping of some implementation defined registers to know the
> status of TBU/TCU operations and some of these registers are not
> accessible in non-secure world such as from kernel and requires SMC
> calls to read them in the secure world. So, add this debug support
> to dump implementation defined registers for TLB sync timeout issues.
>=20
> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> ---
>=20
> Changes in v2:
> =C2=A0* Use scm call consistently so that it works on older chipsets wher=
e
> =C2=A0=C2=A0 some of these regs are secure registers.
> =C2=A0* Add device specific data to get the implementation defined regist=
er
> =C2=A0=C2=A0 offsets.
>=20
> ---
> =C2=A0drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 161 ++++++++++++++++++=
---
> =C2=A0drivers/iommu/arm/arm-smmu/arm-smmu.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
 |=C2=A0=C2=A0 2 +
> =C2=A0drivers/iommu/arm/arm-smmu/arm-smmu.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
 |=C2=A0=C2=A0 1 +
> =C2=A03 files changed, 146 insertions(+), 18 deletions(-)

Hi Sai, and thanks for this patch !

I've encountered TLB sync timeouts with msm8939 SoC recently.
What would be needed to add to this patch so this SoC is supported ?
Like, where could one check the values to be used in an equivalent
of qcom_smmu_impl0_reg_offset values for this SoC (if any change needed) ?
Current values are not found by simply greping in downstream/vendor dtsi/dt=
s files...