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Date:   Thu, 9 Jun 2022 09:59:08 +0200
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Subject: Re: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root
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To:     Bjorn Helgaas <helgaas@kernel.org>,
        Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
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References: <20220608191437.GA411770@bhelgaas>
From:   Michal Simek <michal.simek@xilinx.com>
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On 6/8/22 21:14, Bjorn Helgaas wrote:
> On Wed, Jun 08, 2022 at 10:10:46PM +0530, Bharat Kumar Gogada wrote:
>> Xilinx Versal Premium series has CPM5 block which supports Root Port
>> functioning at Gen5 speed.
>>
>> Xilinx Versal CPM5 has few changes with existing CPM block.
>> - CPM5 has dedicated register space for control and status registers.
>> - CPM5 legacy interrupt handling needs additional register bit
>>    to enable and handle legacy interrupts.
>>
>> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
>> ---
>>   drivers/pci/controller/pcie-xilinx-cpm.c | 33 +++++++++++++++++++++++-
>>   1 file changed, 32 insertions(+), 1 deletion(-)
> 
> Per MAINTAINERS, xilinx-cpm lacks a maintainer.  Can we get one?

Bharat should become maintainer for this driver.

My fragment should cover xilinx things in general in case Bharat is not available.

Thanks,
Michal