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[46.114.4.246]) by smtp.gmail.com with ESMTPSA id y6-20020adfee06000000b0021004d7d75asm25498970wrn.84.2022.06.09.09.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 09:12:05 -0700 (PDT) Date: Thu, 9 Jun 2022 18:12:03 +0200 From: Markus Schneider-Pargmann To: Christophe JAILLET Cc: Fabien Parent , Matthias Brugger , Alexandre Bailon , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] soc: mediatek: add support of MTK_SCPD_STRICT_BUSP cap Message-ID: <20220609161203.o33ydagex5r7pgd2@blmsp> References: <20220530204214.913251-1-fparent@baylibre.com> <20220530204214.913251-3-fparent@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Christophe, On Tue, May 31, 2022 at 07:17:08PM +0200, Christophe JAILLET wrote: > Le 30/05/2022 à 22:42, Fabien Parent a écrit : > > From: Alexandre Bailon > > > > This adds support of MTK_SCPD_STRICT_BUSP cap. > > This is required by the mt8365, for the MM power domain. > > > > Signed-off-by: Alexandre Bailon > > Signed-off-by: Fabien Parent > > --- > > drivers/soc/mediatek/mtk-pm-domains.c | 37 ++++++++++++++++++++------- > > drivers/soc/mediatek/mtk-pm-domains.h | 1 + > > 2 files changed, 29 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c > > index 90b91b3b19a8..beaa5785fda2 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.c > > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > > @@ -263,17 +263,36 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); > > regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > > - ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); > > - if (ret) > > - goto err_pwr_ack; > > + if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUSP)) { > > + /* > > + * In few Mediatek platforms(e.g. MT6779), the bus protect > > + * policy is stricter, which leads to bus protect release must > > + * be prior to bus access. > > + */ > > + ret = scpsys_sram_enable(pd); > > + if (ret < 0) > > + goto err_pwr_ack; > > Hi, > with this new path, the error handling path looks odd because the order of > operation is not the same. True, thank you. I am taking over this series and will fix it for v2. Best, Markus > > > - ret = scpsys_sram_enable(pd); > > - if (ret < 0) > > - goto err_disable_subsys_clks; > > + ret = scpsys_bus_protect_disable(pd); > > + if (ret < 0) > > + goto err_pwr_ack; > > Here... > > > - ret = scpsys_bus_protect_disable(pd); > > - if (ret < 0) > > - goto err_disable_sram; > > + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); > > + if (ret < 0) > > + goto err_pwr_ack; > > ... and here as well. > > CJ > > > + } else { > > + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); > > + if (ret) > > + goto err_pwr_ack; > > + > > + ret = scpsys_sram_enable(pd); > > + if (ret < 0) > > + goto err_disable_subsys_clks; > > + > > + ret = scpsys_bus_protect_disable(pd); > > + if (ret < 0) > > + goto err_disable_sram; > > + } > > return 0; > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h > > index a3955d960233..5347471bc3c4 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.h > > +++ b/drivers/soc/mediatek/mtk-pm-domains.h > > @@ -8,6 +8,7 @@ > > #define MTK_SCPD_SRAM_ISO BIT(2) > > #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) > > #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) > > +#define MTK_SCPD_STRICT_BUSP BIT(5) > > #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) > > #define SPM_VDE_PWR_CON 0x0210 >