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From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
To:     chenhuacai@kernel.org
Cc:     kernel@xen0n.name, maz@kernel.org, linux-kernel@vger.kernel.org,
        Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH for-5.19 v2 2/2] loongarch: Mask out higher bits for cpuid and rename the function
Date:   Thu,  9 Jun 2022 18:52:42 +0100
Message-Id: <20220609175242.977-2-jiaxun.yang@flygoat.com>
In-Reply-To: <20220609175242.977-1-jiaxun.yang@flygoat.com>
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Only low 9 bits of CPUID CSR represents coreid, higher bits
are marked as reserved. In case Loongson may define higher
bits in future, just mask them out for get_csr_cpuid.

Also, as we already have read_csr_cpuid, rename get_csr_cpuid
to get_csr_coreid to reflect the actual bit domain name.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/loongarch/include/asm/loongarch.h | 4 ++--
 drivers/irqchip/irq-loongson-liointc.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 3ba4f7e87cd2..fe2408144fa3 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1198,9 +1198,9 @@ static inline u64 drdtime(void)
 	return val;
 }
 
-static inline unsigned int get_csr_cpuid(void)
+static inline unsigned int get_csr_coreid(void)
 {
-	return csr_read32(LOONGARCH_CSR_CPUID);
+	return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
 }
 
 static inline void csr_any_send(unsigned int addr, unsigned int data,
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8d05d8bcf56f..2ee636b2d827 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -42,7 +42,7 @@
 #if defined(CONFIG_MIPS)
 #define liointc_core_id get_ebase_cpunum()
 #else
-#define liointc_core_id get_csr_cpuid()
+#define liointc_core_id read_csr_cpuid()
 #endif
 
 struct liointc_handler_data {
-- 
2.25.1