Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Fri, 10 Jun 2022 09:02:11 +0100
Message-ID: <874k0t3q0s.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc:     chenhuacai@kernel.org, kernel@xen0n.name,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH for-5.19 v2 2/2] loongarch: Mask out higher bits for cpuid and rename the function
In-Reply-To: <20220609175242.977-2-jiaxun.yang@flygoat.com>
References: <20220609175242.977-1-jiaxun.yang@flygoat.com>
        <20220609175242.977-2-jiaxun.yang@flygoat.com>
User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue)
 FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1
 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO)
MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue")
Content-Type: text/plain; charset=US-ASCII
Precedence: bulk

On Thu, 09 Jun 2022 18:52:42 +0100,
Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> 
> Only low 9 bits of CPUID CSR represents coreid, higher bits
> are marked as reserved. In case Loongson may define higher
> bits in future, just mask them out for get_csr_cpuid.
> 
> Also, as we already have read_csr_cpuid, rename get_csr_cpuid
> to get_csr_coreid to reflect the actual bit domain name.

I assume you meant read_csr_cpuid here?

> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/loongarch/include/asm/loongarch.h | 4 ++--
>  drivers/irqchip/irq-loongson-liointc.c | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 3ba4f7e87cd2..fe2408144fa3 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -1198,9 +1198,9 @@ static inline u64 drdtime(void)
>  	return val;
>  }
>  
> -static inline unsigned int get_csr_cpuid(void)
> +static inline unsigned int get_csr_coreid(void)
>  {
> -	return csr_read32(LOONGARCH_CSR_CPUID);
> +	return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
>  }
>  
>  static inline void csr_any_send(unsigned int addr, unsigned int data,
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 8d05d8bcf56f..2ee636b2d827 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -42,7 +42,7 @@
>  #if defined(CONFIG_MIPS)
>  #define liointc_core_id get_ebase_cpunum()
>  #else
> -#define liointc_core_id get_csr_cpuid()
> +#define liointc_core_id read_csr_cpuid()
>  #endif
>  
>  struct liointc_handler_data {

I'm not going to take this patch as part of 5.19, as loongarch doesn't
have any irqchip support yet, and this can be made part of the IRQ
enabling series if really necessary.

	M.

-- 
Without deviation from the norm, progress is not possible.