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Date:   Fri, 10 Jun 2022 13:24:40 +0300
From:   Serge Semin <fancer.lancer@gmail.com>
To:     Sergey Shtylyov <s.shtylyov@omp.ru>
Cc:     Serge Semin <Sergey.Semin@baikalelectronics.ru>,
        Stephen Boyd <sboyd@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Michael Turquette <mturquette@baylibre.com>,
        Luca Ceresoli <luca@lucaceresoli.net>,
        Marek Vasut <marek.vasut@gmail.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-clk@vger.kernel.org, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org, Stephen Boyd <sboyd@codeaurora.org>
Subject: Re: [PATCH v4 2/8] clk: vc5: Fix 5P49V6901 outputs disabling when
 enabling FOD
Message-ID: <20220610102440.ubejkcbkwb7wgah6@mobilestation>
References: <20220610072124.8714-1-Sergey.Semin@baikalelectronics.ru>
 <20220610072124.8714-3-Sergey.Semin@baikalelectronics.ru>
 <eb0cbc41-2868-4cbf-9fbf-eeabd25dda04@omp.ru>
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On Fri, Jun 10, 2022 at 01:03:10PM +0300, Sergey Shtylyov wrote:
> On 6/10/22 10:21 AM, Serge Semin wrote:
> 
> > We have discovered random glitches during the system boot up procedure.
> > The problem investigation led us to the weird outcomes: when none of the
> > Renesas 5P49V6901 ports are explicitly enabled by the kernel driver, the
> > glitches disappeared. It was a mystery since the SoC external clock
> > domains were fed with different 5P49V6901 outputs. The driver code didn't
> > seem like bogus either. We almost despaired to find out a root cause when
> > the solution was found for a more modern revision of the chip. It turned
> > out the 5P49V6901 clock generator stopped its output for a short period of
> > time during the VC5_OUT_DIV_CONTROL register writing. The same problem has
> > was found for the 5P49V6965 revision of the chip and the was successfully
> 

>    s/was found/been found/, s/the was/that was/?

Right. Thanks.)

-Sergey

> 
> > fixed in commit fc336ae622df ("clk: vc5: fix output disabling when
> > enabling a FOD") by enabling the "bypass_sync" flag hidden inside "Unused
> > Factory Reserved Register". Even though the 5P49V6901 registers
> > description and programming guide doesn't provide any intel regarding that
> > flag, setting it up anyway in the officially unused register completely
> > eliminated the denoted glitches. Thus let's activate the functionality
> > submitted in commit fc336ae622df ("clk: vc5: fix output disabling when
> > enabling a FOD") for the Renesas 5P49V6901 chip too in order to remove
> > the ports implicit inter-dependency.
> > 
> > Fixes: dbf6b16f5683 ("clk: vc5: Add support for IDT VersaClock 5P49V6901")
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> [...]
> 
> MBR, Sergey