Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Liu Ying <victor.liu@nxp.com>
To:     dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-media@vger.kernel.org
Cc:     andrzej.hajda@intel.com, narmstrong@baylibre.com,
        robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com,
        jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie,
        daniel@ffwll.ch, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
        s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
        linux-imx@nxp.com, lee.jones@linaro.org, mchehab@kernel.org,
        marcel.ziswiler@toradex.com, Rob Herring <robh@kernel.org>
Subject: [PATCH v9 13/14] dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding
Date:   Sat, 11 Jun 2022 22:14:20 +0800
Message-Id: <20220611141421.718743-14-victor.liu@nxp.com>
In-Reply-To: <20220611141421.718743-1-victor.liu@nxp.com>
References: <20220611141421.718743-1-victor.liu@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Q2kCy9Z0mGlkxGkurBSxDOb5RvpjMSIfDrTfv8sxrQqv3r6S5N+CLy2OIPFF?=
 =?us-ascii?Q?9Fai06LgRcDNkuJMu7OQcRloASlXWrCgl42OepA6QvVB7hlEYBW8VcWdzwr8?=
 =?us-ascii?Q?18qS8UpjgZp4hP69mv+60ZnKmHBbShEChcq2BHB10DDvu0SWcpi+ZEJvl/nz?=
 =?us-ascii?Q?KMpTJ8nFU8NxmnMx5vAmo2I8lxQvAxAhOHEK5m8K7fRkb6tIfT60EOXe/dUm?=
 =?us-ascii?Q?e59DOgRqxncqoYBI6zs6VCt9ldvZ6X7mc+/AhS3gYkym4CEJ75nmC/IvwioD?=
 =?us-ascii?Q?Q0a1ko/O4RSxj7u3gOIGEGBcTP7Spa3hCagjJHb5MsKxSslbR+Qzjwx0ykkX?=
 =?us-ascii?Q?c4plplRunvISz0yf7Kdw1jCTPrK7EXrJ1B3qy9/Ty3SUNBzbl9R2Uf1rUPLG?=
 =?us-ascii?Q?HfHZeEA8qffQ8xdbsO6M1W/MRe/DUjZnQtVp9ijmJcT32Ry8WWFbrAg1bFKm?=
 =?us-ascii?Q?qeJskOl7CvxAOdH4Ntf4g4RU8gQmvzRzbZCw/+/lokT2RSdOflUTcE20MpEJ?=
 =?us-ascii?Q?2EvkclcnDzcu9pAiAnmybTz4mZNF0MJsEcuUaHXEhEQ6XDvIa7E2zjMgO7z8?=
 =?us-ascii?Q?GfAfPcXKLXiklZ62bozgk+/1lhGzGgZ69c8LkuGSBN446Wo6hzh2imn9iLPg?=
 =?us-ascii?Q?tVwpO2HbwgMiDxLwLVSYoC9rhvvAdHX5xbLWgHUK450OOQnVLl7xkQ92+cJ9?=
 =?us-ascii?Q?AIYCDkeYkRBEr8P0S2lOHU73i9Hsy4CHJpMf2hwlrobkXqIPaCQd+QR3Hcxl?=
 =?us-ascii?Q?D2XTCxWq85fUknjliWavrcwoQHW44zdodeAX9JIZI51kyokt4QJ63MbflxdU?=
 =?us-ascii?Q?mJtC0xUTc7wl67TbQWhEXtVpPXui+rm2mknoirH0C02152idFUR06bYZTGuG?=
 =?us-ascii?Q?mCKdFJyiW9hWitVgAP8qn4VhAso8Ef0F2EaeX66uQ6HXi31ec/35wFK+9eE3?=
 =?us-ascii?Q?youpZqj0wbrh7yhmEs1ebI77V9nDx8SqH56gP2C6LeR9xG+OSHz3JwR/gYtT?=
 =?us-ascii?Q?4mSx7+EFaDBJO4sct5+3FRHBm8IjD7/wwkFgyGzBtwKyiy2lEYXmpw1O9gC8?=
 =?us-ascii?Q?jH3KMNfraNcnOUxwfZik9FYHmAj7wSqdJ/wGmuN4pt9gNUm5ZjReLehq47jY?=
 =?us-ascii?Q?LmfTfoOZmAb7LTyyOJvl+ywtI4P83+2UYrELO7c7noea82Jt2zqfLFVdurnU?=
 =?us-ascii?Q?8FDGE0iEqGGcVtbc5QhibByp7hbmlmA8gx36omyw6clS32mGdcmmne06nTtn?=
 =?us-ascii?Q?tN9RodwXB+viwTOc6eBJU0cZeQ9D6ui0e7PDJjLMMooZdVw82nmJLn9JB0Qg?=
 =?us-ascii?Q?z4FWTcLKeL8pBO2d9cGjZoXuj228NHbn7n54cC31K2lTvgtLNFCj/3uagzxX?=
 =?us-ascii?Q?8R+ebAZsZuHJmgF3TAgC2t7uBKR7tLK8Mf0X2fkLIWBA0aHoiErwS1KZBL1Q?=
 =?us-ascii?Q?eSTo6M5ezXfOj4jZf1N0qqbt4oWj6dHluDRi3uOzYYzWmDAg3u6rErLyp+/p?=
 =?us-ascii?Q?GP67n6dIQHvjQy5gOyYJGgasuxx5CNL8Ju5Wqz9tEtJF8uYLAsBlZjXhs9Sg?=
 =?us-ascii?Q?TW4HGP6w29Qgwa6QeP7e4vdDEM7gprKyDObttH7ot+7ef0HVfZWQyXxMBcp+?=
 =?us-ascii?Q?IkbyhfDKgWQFPbFlTvblET1mBUOqrv5645TBHXNx510C0bVCRbhmI33rqTBc?=
 =?us-ascii?Q?6nNZnqAovgf2zRqvLsTvx4oa/wF0Ju1AgOkvd3+mB9GYUB0r4oAM0W3Zj1Ew?=
 =?us-ascii?Q?l2AcOFwzXQ=3D=3D?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 6a86b0e2-3157-4b18-0272-08da4bb4aa73
X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2022 14:14:15.3613
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: h9qSFs9uQZvWzlmCpjxL4iz+QF4mFJLDfxVugkuGN2Kcz2iCXU6pv9cQlKK6bQZGouV0CnCMZDULP6cXt8Pobg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8249
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v8->v9:
* No change.

v7->v8:
* No change.

v6->v7:
* Add Rob's R-b tag.

v5->v6:
* Drop 'select' schema. (Rob)

v4->v5:
* Newly introduced in v5. (Rob)

 .../bindings/mfd/fsl,imx8qxp-csr.yaml         | 192 ++++++++++++++++++
 1 file changed, 192 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml

diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
new file mode 100644
index 000000000000..f09577105b50
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  As a system controller, the Freescale i.MX8qm/qxp Control and Status
+  Registers(CSR) module represents a set of miscellaneous registers of a
+  specific subsystem.  It may provide control and/or status report interfaces
+  to a mix of standalone hardware devices within that subsystem.  One typical
+  use-case is for some other nodes to acquire a reference to the syscon node
+  by phandle, and the other typical use-case is that the operating system
+  should consider all subnodes of the CSR module as separate child devices.
+
+properties:
+  $nodename:
+    pattern: "^syscon@[0-9a-f]+$"
+
+  compatible:
+    items:
+      - enum:
+          - fsl,imx8qxp-mipi-lvds-csr
+          - fsl,imx8qm-lvds-csr
+      - const: syscon
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: ipg
+
+patternProperties:
+  "^(ldb|phy|pxl2dpi)$":
+    type: object
+    description: The possible child devices of the CSR module.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8qxp-mipi-lvds-csr
+    then:
+      required:
+        - pxl2dpi
+        - ldb
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8qm-lvds-csr
+    then:
+      required:
+        - phy
+        - ldb
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8-lpcg.h>
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    mipi_lvds_0_csr: syscon@56221000 {
+        compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+        reg = <0x56221000 0x1000>;
+        clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+        clock-names = "ipg";
+
+        mipi_lvds_0_pxl2dpi: pxl2dpi {
+            compatible = "fsl,imx8qxp-pxl2dpi";
+            fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+            power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+                    reg = <0>;
+
+                    mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+                        reg = <0>;
+                        remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
+                    };
+
+                    mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
+                        reg = <1>;
+                        remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
+                    };
+                };
+
+                port@1 {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+                    reg = <1>;
+
+                    mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+                        reg = <0>;
+                        remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+                    };
+
+                    mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+                        reg = <1>;
+                        remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+                    };
+                };
+            };
+        };
+
+        mipi_lvds_0_ldb: ldb {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            compatible = "fsl,imx8qxp-ldb";
+            clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+                     <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+            clock-names = "pixel", "bypass";
+            power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+            channel@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0>;
+                phys = <&mipi_lvds_0_phy>;
+                phy-names = "lvds_phy";
+
+                port@0 {
+                    reg = <0>;
+
+                    mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+                        remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+
+                    /* ... */
+                };
+            };
+
+            channel@1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <1>;
+                phys = <&mipi_lvds_0_phy>;
+                phy-names = "lvds_phy";
+
+                port@0 {
+                    reg = <0>;
+
+                    mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+                        remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+
+                    /* ... */
+                };
+            };
+        };
+    };
+
+    mipi_lvds_0_phy: phy@56228300 {
+        compatible = "fsl,imx8qxp-mipi-dphy";
+        reg = <0x56228300 0x100>;
+        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+        clock-names = "phy_ref";
+        #phy-cells = <0>;
+        fsl,syscon = <&mipi_lvds_0_csr>;
+        power-domains = <&pd IMX_SC_R_MIPI_0>;
+    };
-- 
2.25.1