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Message-ID: <ded0e4f1-ed94-7518-f190-ed7aff1bc832@nvidia.com>
Date:   Mon, 13 Jun 2022 13:32:11 +0530
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Subject: Re: [PATCH v4 06/18] PCI: dwc: Enable CDM-check independently from
 the num_lanes value
Content-Language: en-US
To:     Serge Semin <Sergey.Semin@baikalelectronics.ru>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Jingoo Han <jingoohan1@gmail.com>,
        Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
        =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>,
        Thierry Reding <treding@nvidia.com>
Cc:     Serge Semin <fancer.lancer@gmail.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
        Frank Li <Frank.Li@nxp.com>,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru>
 <20220610082535.12802-7-Sergey.Semin@baikalelectronics.ru>
From:   Vidya Sagar <vidyas@nvidia.com>
In-Reply-To: <20220610082535.12802-7-Sergey.Semin@baikalelectronics.ru>
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Thanks for pushing this change.

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>

On 6/10/2022 1:55 PM, Serge Semin wrote:
> External email: Use caution opening links or attachments
> 
> 
> Currently the embedded CDM IOs consistency check-engine is enabled only if
> the num_lanes field of dw_pcie structure is set to non-zero value. It's
> definitely wrong since the CDM checking has nothing to do with the PCIe
> lanes settings, while that feature will be left disabled for the platforms
> which expect it being enabled and prefer keeping the default lanes setup.
> Let's fix that by enabling the CDM-check feature before the num_lanes
> parameter is handled.
> 
> Fixes: 07f123def73e ("PCI: dwc: Add support to enable CDM register check")
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on v4 lap of the series.
> ---
>   drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 347251bf87d0..5848cc520b52 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -740,6 +740,13 @@ void dw_pcie_setup(struct dw_pcie *pci)
>          val |= PORT_LINK_DLL_LINK_EN;
>          dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> 
> +       if (of_property_read_bool(np, "snps,enable-cdm-check")) {
> +               val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
> +               val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
> +                      PCIE_PL_CHK_REG_CHK_REG_START;
> +               dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
> +       }
> +
>          of_property_read_u32(np, "num-lanes", &pci->num_lanes);
>          if (!pci->num_lanes) {
>                  dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> @@ -786,11 +793,4 @@ void dw_pcie_setup(struct dw_pcie *pci)
>                  break;
>          }
>          dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> -
> -       if (of_property_read_bool(np, "snps,enable-cdm-check")) {
> -               val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
> -               val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
> -                      PCIE_PL_CHK_REG_CHK_REG_START;
> -               dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
> -       }
>   }
> --
> 2.35.1
>