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[2620:137:e000::1:20]) by mx.google.com with ESMTP id nd6-20020a170907628600b006fef110c5a4si12552606ejc.968.2022.06.14.09.01.36; Tue, 14 Jun 2022 09:02:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=B5nStvmi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344457AbiFNPdy (ORCPT + 99 others); Tue, 14 Jun 2022 11:33:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245380AbiFNPdv (ORCPT ); Tue, 14 Jun 2022 11:33:51 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E298D2A27C; Tue, 14 Jun 2022 08:33:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1655220831; x=1686756831; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=nsB3eYexNBUcGw9y7BgsFdoShmBCDzBchVtEo4Wo/Ok=; b=B5nStvmiWrKRQJEWWsE6OVKTr8yea8uUpZEMSq3Q5b0HmuwvqwLdcE7e 5Iv4/rS3mlDFWVK/UbelPAiPNtloLEtPdPSK7iQwewnmN0m0Os2fdJe3+ u82UhBhWpiybd7BceolMdYCvGXPGYt0qb0HvzB3MTMPyWEZb7rwh7zNJr 0=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 14 Jun 2022 08:33:50 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2022 08:33:49 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 14 Jun 2022 08:33:49 -0700 Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 14 Jun 2022 08:33:45 -0700 From: Taniya Das To: Stephen Boyd , =?UTF-8?q?Michael=20Turquette=20=C2=A0?= , Bjorn Andersson CC: , , , , , , , Taniya Das Subject: [PATCH v5 2/3] dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280 Date: Tue, 14 Jun 2022 21:03:05 +0530 Message-ID: <20220614153306.29339-3-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220614153306.29339-1-quic_tdas@quicinc.com> References: <20220614153306.29339-1-quic_tdas@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Support external mclk to interface external MI2S clocks for SC7280. Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280"). Acked-by: Rob Herring Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h index 28ed2a07aacc..0324c69ce968 100644 --- a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h @@ -19,6 +19,8 @@ #define LPASS_CORE_CC_LPM_CORE_CLK 9 #define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10 #define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11 +#define LPASS_CORE_CC_EXT_MCLK0_CLK 12 +#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 13 /* LPASS_CORE_CC power domains */ #define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0 -- 2.17.1