Received: by 2002:a6b:fb09:0:0:0:0:0 with SMTP id h9csp457414iog; Wed, 15 Jun 2022 05:56:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpTWUt05H/PfnBIuKTpTU5IuiXMwgoKXrBfHE5+uL7PLVkRuotfJ+FA0Q5CZRZCtBSCayX X-Received: by 2002:a05:6a00:2349:b0:51c:29c0:82f6 with SMTP id j9-20020a056a00234900b0051c29c082f6mr10112854pfj.32.1655297769779; Wed, 15 Jun 2022 05:56:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1655297769; cv=none; d=google.com; s=arc-20160816; b=ev+sq0NexRGXLzu0gq7VPI771972KeTfujVoQDfcfOKFrcjL8YcF1btCM3kPZrbL+w By7PTvMg9Bf9Qnq10B3ekvqoMOZQ938nkKJMKYJybFNmTHtF0vZA2so4zckQW2Qbuyfk F2aVdyqBffaibLZSq88wHj/cqLe+P13mWbSrvGlfBvolM2Axy9AQnW2BbrWamrKsu4wq GnlwWbe8uhYv8J8aKZ/LrAeg05QnfNVi+GTvqx57ttaF6kksXoQPvlSDCGEExoJwbMle Amzb8lg7qgLkE5YFKIu22GkKdylvgBh54MQeyEJLBomj0oVzJjwHMONSfvpZCTqWUkAN vGZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to :organization:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:dkim-signature; bh=KpVHzKcmMluNecmqJsOrjs7/3YHWI5DsUiReNFUoabo=; b=I5ojWKXCTWARZf7qpC6q3BoKq0JJv5FXJXlUf2xvYCO/nlmwFilsV0toMZ20UDjww+ zeYyZpilncWXQTL6aAKP1b+6cW6CvpzNHCjVolb6ohPmh0Z3Hwk+fLj10WKtxO85haIL sC/wPVvN2nIGww1/f7WCf8RO4qMhb9F+5IZaYFwV1yuw7Ft1RTxrD7OF4gQkEOURr2Wg VY7aMZu3J7HLw1ITw06tvWeRmuDiY8BQe+TpaRRYFHIQoThrwejN/2UViEQMSI2coaPO 9NjiUfsnauuV5E8iJCq5nQVh2orVnAHvz9rfBRt5k7ILZBkBa4RU7MsrBKTyudp5AR9f 3kHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eYDypMz+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y21-20020a056a00191500b005206b82a13esi4280013pfi.127.2022.06.15.05.55.58; Wed, 15 Jun 2022 05:56:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eYDypMz+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348727AbiFOMxj (ORCPT + 99 others); Wed, 15 Jun 2022 08:53:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240337AbiFOMxS (ORCPT ); Wed, 15 Jun 2022 08:53:18 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2A0D14D3E; Wed, 15 Jun 2022 05:53:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655297597; x=1686833597; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=d4YTN2oJ2wEg9km7RqOmzcHYPAYIj901Sf+UmvzSgSM=; b=eYDypMz+7tRMP2+S+eX4T0jVmdi3xpEC0bKKjR0A+8pOXW4zLCfti3lh jQskBBtxciyErXtdD/xYxSaeNaj31RWWX3pkJWZDDjixD3/9h3e4RMQYB FWnLBIN0/OUylBTqa55lnZwh2sN14zVralc3BzcMowTVPvdSUzvGY46ME tjiEi1wL6gki6tLZLuAcizCViqKa+y6JfD/yKe1jg9LxYkog8k2RgXm1X OWJEAZmt8yrpbI3arsvaqRRsAkF9pDpRLAW1Kt84x6wwOFUmzn4R7W/EF hW0yqOjW0WKkVT2UuWWqUq5p0lUsoDvG06y4fFxg6oWWLYcJ1UNgoNc6o A==; X-IronPort-AV: E=McAfee;i="6400,9594,10378"; a="258802197" X-IronPort-AV: E=Sophos;i="5.91,302,1647327600"; d="scan'208";a="258802197" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2022 05:52:27 -0700 X-IronPort-AV: E=Sophos;i="5.91,302,1647327600"; d="scan'208";a="911641796" Received: from nhanraha-mobl1.ger.corp.intel.com (HELO [10.213.196.47]) ([10.213.196.47]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2022 05:52:23 -0700 Message-ID: Date: Wed, 15 Jun 2022 13:52:21 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v3 2/2] drm/msm: Expose client engine utilization via fdinfo Content-Language: en-US To: Rob Clark , dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Thomas Zimmermann , Chris Healy , Rob Clark , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Jonathan Corbet , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , "open list:DOCUMENTATION" , open list References: <20220609174213.2265938-1-robdclark@gmail.com> <20220609174213.2265938-2-robdclark@gmail.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc In-Reply-To: <20220609174213.2265938-2-robdclark@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HK_RANDOM_ENVFROM,HK_RANDOM_FROM, NICE_REPLY_A,RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/06/2022 18:42, Rob Clark wrote: > From: Rob Clark > > Similar to AMD commit > 874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the > infrastructure added in previous patches, we add basic client info > and GPU engine utilisation for msm. > > Example output: > > # cat /proc/`pgrep glmark2`/fdinfo/6 > pos: 0 > flags: 02400002 > mnt_id: 21 > ino: 162 > drm-driver: msm > drm-client-id: 7 > drm-engine-gpu: 1734371319 ns > drm-cycles-gpu: 1153645024 > drm-maxfreq-gpu: 800000000 Hz > > See also: https://patchwork.freedesktop.org/patch/468505/ > > v2: Add dev-maxfreq-$engine and update drm-usage-stats.rst > v3: spelling and compiler warning > > Signed-off-by: Rob Clark > --- > Documentation/gpu/drm-usage-stats.rst | 21 +++++++++++++++++++++ > drivers/gpu/drm/msm/msm_drv.c | 19 ++++++++++++++++++- > drivers/gpu/drm/msm/msm_gpu.c | 21 +++++++++++++++++++-- > drivers/gpu/drm/msm/msm_gpu.h | 19 +++++++++++++++++++ > 4 files changed, 77 insertions(+), 3 deletions(-) > > diff --git a/Documentation/gpu/drm-usage-stats.rst b/Documentation/gpu/drm-usage-stats.rst > index 6c9f166a8d6f..92c5117368d7 100644 > --- a/Documentation/gpu/drm-usage-stats.rst > +++ b/Documentation/gpu/drm-usage-stats.rst > @@ -105,6 +105,27 @@ object belong to this client, in the respective memory region. > Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB' > indicating kibi- or mebi-bytes. > > +- drm-cycles- > + > +Engine identifier string must be the same as the one specified in the > +drm-engine- tag and shall contain the number of busy cycles for the given > +engine. > + > +Values are not required to be constantly monotonic if it makes the driver > +implementation easier, but are required to catch up with the previously reported > +larger value within a reasonable period. Upon observing a value lower than what > +was previously read, userspace is expected to stay with that larger previous > +value until a monotonic update is seen. > + > +- drm-maxfreq- [Hz|MHz|KHz] Kilo should be lowercase, I *think*. Simplify and only document Hz? > + > +Engine identifier string must be the same as the one specified in the > +drm-engine- tag and shall contain the maximum frequency for the given > +engine. Taken together with drm-cycles-, this can be used to calculate > +percentage utilization of the engine, whereas drm-engine- only reflects > +time active without considering what frequency the engine is operating as a > +percentage of it's maximum frequency. Slipped my mind to reply to v3.. Acked-by: Tvrtko Ursulin Regards, Tvrtko > + > =============================== > Driver specific implementations > =============================== > diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c > index 14ab9a627d8b..57a66093e671 100644 > --- a/drivers/gpu/drm/msm/msm_drv.c > +++ b/drivers/gpu/drm/msm/msm_drv.c > @@ -948,7 +948,24 @@ static const struct drm_ioctl_desc msm_ioctls[] = { > DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), > }; > > -DEFINE_DRM_GEM_FOPS(fops); > +static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f) > +{ > + struct drm_file *file = f->private_data; > + struct drm_device *dev = file->minor->dev; > + struct msm_drm_private *priv = dev->dev_private; > + struct drm_printer p = drm_seq_file_printer(m); > + > + if (!priv->gpu) > + return; > + > + msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p); > +} > + > +static const struct file_operations fops = { > + .owner = THIS_MODULE, > + DRM_GEM_FOPS, > + .show_fdinfo = msm_fop_show_fdinfo, > +}; > > static const struct drm_driver msm_driver = { > .driver_features = DRIVER_GEM | > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > index 244511f85044..f99292eaf529 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.c > +++ b/drivers/gpu/drm/msm/msm_gpu.c > @@ -4,6 +4,8 @@ > * Author: Rob Clark > */ > > +#include "drm/drm_drv.h" > + > #include "msm_gpu.h" > #include "msm_gem.h" > #include "msm_mmu.h" > @@ -146,6 +148,16 @@ int msm_gpu_pm_suspend(struct msm_gpu *gpu) > return 0; > } > > +void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx, > + struct drm_printer *p) > +{ > + drm_printf(p, "drm-driver:\t%s\n", gpu->dev->driver->name); > + drm_printf(p, "drm-client-id:\t%u\n", ctx->seqno); > + drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns); > + drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles); > + drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate); > +} > + > int msm_gpu_hw_init(struct msm_gpu *gpu) > { > int ret; > @@ -652,7 +664,7 @@ static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > { > int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; > volatile struct msm_gpu_submit_stats *stats; > - u64 elapsed, clock = 0; > + u64 elapsed, clock = 0, cycles; > unsigned long flags; > > stats = &ring->memptrs->stats[index]; > @@ -660,12 +672,17 @@ static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; > do_div(elapsed, 192); > > + cycles = stats->cpcycles_end - stats->cpcycles_start; > + > /* Calculate the clock frequency from the number of CP cycles */ > if (elapsed) { > - clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000; > + clock = cycles * 1000; > do_div(clock, elapsed); > } > > + submit->queue->ctx->elapsed_ns += elapsed; > + submit->queue->ctx->cycles += cycles; > + > trace_msm_gpu_submit_retired(submit, elapsed, clock, > stats->alwayson_start, stats->alwayson_end); > > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index 6def00883046..4911943ba53b 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -361,6 +361,22 @@ struct msm_file_private { > /** cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE */ > char *cmdline; > > + /** > + * elapsed: > + * > + * The total (cumulative) elapsed time GPU was busy with rendering > + * from this context in ns. > + */ > + uint64_t elapsed_ns; > + > + /** > + * cycles: > + * > + * The total (cumulative) GPU cycles elapsed attributed to this > + * context. > + */ > + uint64_t cycles; > + > /** > * entities: > * > @@ -544,6 +560,9 @@ static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) > int msm_gpu_pm_suspend(struct msm_gpu *gpu); > int msm_gpu_pm_resume(struct msm_gpu *gpu); > > +void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx, > + struct drm_printer *p); > + > int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); > struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, > u32 id);