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Message-ID: <1e92745e-6fa4-a3bd-d0cb-5c1f78efbead@quicinc.com>
Date:   Wed, 15 Jun 2022 18:44:19 +0530
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Subject: Re: [PATCH v1] PCI: qcom: Allow L1 and its sub states on qcom dwc
 wrapper
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To:     Stephen Boyd <swboyd@chromium.org>, <helgaas@kernel.org>
CC:     <linux-pci@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <quic_vbadigan@quicinc.com>,
        <quic_hemantk@quicinc.com>, <quic_ramkri@quicinc.com>,
        <manivannan.sadhasivam@linaro.org>, Andy Gross <agross@kernel.org>,
        "Bjorn Andersson" <bjorn.andersson@linaro.org>,
        Stanimir Varbanov <svarbanov@mm-sol.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        "Rob Herring" <robh@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>
References: <1654240730-31322-1-git-send-email-quic_krichai@quicinc.com>
 <CAE-0n52hpKxMG=gq1rPGx0cM2VKNRo+WHVW+ExCScJ8UwZKgGA@mail.gmail.com>
From:   Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
In-Reply-To: <CAE-0n52hpKxMG=gq1rPGx0cM2VKNRo+WHVW+ExCScJ8UwZKgGA@mail.gmail.com>
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On 6/9/2022 3:47 AM, Stephen Boyd wrote:
> Quoting Krishna chaitanya chundru (2022-06-03 00:18:50)
>> Allow L1 and its sub-states in the qcom dwc pcie wrapper.
>> By default its disabled. So enable it explicitly.
>>
> Would be good to add some more details about why it's disabled by
> default. I guess it's disabled by default in the hardware and enabling
> it is OK to do unconditionally for all qcom dwc pcie devices?

This is disabled by default in the hardware. We can enable this for all 
qcom devices unconditionally because

Adding this patch alone will not allow aspm transitions we need to 
enable aspm configs. If particular devices doesn't want aspm

they can disable using aspm configs.