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From:   Dao Lu <daolu@rivosinc.com>
Date:   Wed, 15 Jun 2022 10:06:01 -0700
Message-ID: <CAKh7v-TZ3+t+_MRYQSxjbm3qJ6huHO4NBiv2OEMbXB0=4LeRNA@mail.gmail.com>
Subject: Re: [PATCH v2] arch/riscv: add Zihintpause support
To:     =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>
Cc:     linux-kernel@vger.kernel.org,
        "open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Atish Patra <atishp@atishpatra.org>,
        Anup Patel <anup@brainfault.org>,
        Randy Dunlap <rdunlap@infradead.org>,
        Rob Herring <robh@kernel.org>,
        Alexandre Ghiti <alexandre.ghiti@canonical.com>,
        Qinglin Pan <panqinglin2020@iscas.ac.cn>,
        Tsukasa OI <research_trasio@irq.a4lg.com>,
        Jisheng Zhang <jszhang@kernel.org>
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Thanks Heiko and Palmer, will address the comments, rebase and send a v3.

On Tue, Jun 14, 2022 at 9:44 AM Heiko St=C3=BCbner <heiko@sntech.de> wrote:
>
> Am Dienstag, 24. Mai 2022, 23:19:50 CEST schrieb Dao Lu:
> > Implement support for the ZiHintPause extension.
> >
> > The PAUSE instruction is a HINT that indicates the current hart=E2=80=
=99s rate of
> > instruction retirement should be temporarily reduced or paused.
> >
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> > Tested-by: Heiko Stuebner <heiko@sntech.de>
> > Signed-off-by: Dao Lu <daolu@rivosinc.com>
> > ---
> >
> > v1 -> v2:
> >  Remove the usage of static branch, use PAUSE if toolchain supports it
> >
> >  arch/riscv/Makefile                     | 4 ++++
> >  arch/riscv/include/asm/hwcap.h          | 1 +
> >  arch/riscv/include/asm/vdso/processor.h | 8 +++++++-
> >  arch/riscv/kernel/cpu.c                 | 1 +
> >  arch/riscv/kernel/cpufeature.c          | 2 ++
> >  5 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > index 7d81102cffd4..900a8fda1a2d 100644
> > --- a/arch/riscv/Makefile
> > +++ b/arch/riscv/Makefile
> > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C)  :=3D $(riscv-marc=
h-y)c
> >  toolchain-need-zicsr-zifencei :=3D $(call cc-option-yn, -march=3D$(ris=
cv-march-y)_zicsr_zifencei)
> >  riscv-march-$(toolchain-need-zicsr-zifencei) :=3D $(riscv-march-y)_zic=
sr_zifencei
> >
> > +# Check if the toolchain supports Zihintpause extension
> > +toolchain-supports-zihintpause :=3D $(call cc-option-yn, -march=3D$(ri=
scv-march-y)_zihintpause)
> > +riscv-march-$(toolchain-supports-zihintpause) :=3D $(riscv-march-y)_zi=
hintpause
> > +
> >  KBUILD_CFLAGS +=3D -march=3D$(subst fd,,$(riscv-march-y))
> >  KBUILD_AFLAGS +=3D -march=3D$(riscv-march-y)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hw=
cap.h
> > index 0734e42f74f2..caa9ee5459b4 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap;
> >   */
> >  enum riscv_isa_ext_id {
> >       RISCV_ISA_EXT_SSCOFPMF =3D RISCV_ISA_EXT_BASE,
>
> svpbmt got merged meanwhile, so this patch needs a rebase
> onto 5.19-rc.
>
> One more nit below
>
> > +     RISCV_ISA_EXT_ZIHINTPAUSE,
> >       RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX,
> >  };
> >
> > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/inclu=
de/asm/vdso/processor.h
> > index 134388cbaaa1..4de911a25051 100644
> > --- a/arch/riscv/include/asm/vdso/processor.h
> > +++ b/arch/riscv/include/asm/vdso/processor.h
> > @@ -8,7 +8,13 @@
> >
> >  static inline void cpu_relax(void)
> >  {
> > -#ifdef __riscv_muldiv
> > +#ifdef __riscv_zihintpause
> > +     /*
> > +      * Reduce instruction retirement.
> > +      * This assumes the PC changes.
> > +      */
> > +     __asm__ __volatile__ ("pause");
> > +#elif __riscv_muldiv
> >       int dummy;
> >       /* In lieu of a halt instruction, induce a long-latency stall. */
> >       __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy));
> > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> > index ccb617791e56..89e563e9c4cc 100644
> > --- a/arch/riscv/kernel/cpu.c
> > +++ b/arch/riscv/kernel/cpu.c
> > @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node)
> >   */
> >  static struct riscv_isa_ext_data isa_ext_arr[] =3D {
> >       __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> > +     __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> >       __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
> >  };
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeat=
ure.c
> > index 1b2d42d7f589..37ff06682ae6 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -25,6 +25,7 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) _=
_read_mostly;
> >  __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
> >  #endif
> >
> > +
>
> this is an unrelated change and also is adding an unneeded extra empty li=
ne.
>
>
> Heiko
>
> >  /**
> >   * riscv_isa_extension_base() - Get base extension word
> >   *
> > @@ -192,6 +193,7 @@ void __init riscv_fill_hwcap(void)
> >                               set_bit(*ext - 'a', this_isa);
> >                       } else {
> >                               SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT=
_SSCOFPMF);
> > +                             SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_=
EXT_ZIHINTPAUSE);
> >                       }
> >  #undef SET_ISA_EXT_MAP
> >               }
> >
>
>
>
>