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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l3-20020a17090270c300b001639f1759d8si1611355plt.268.2022.06.16.00.31.57; Thu, 16 Jun 2022 00:32:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=f3GF5E0j; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359233AbiFPHZz (ORCPT + 99 others); Thu, 16 Jun 2022 03:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359190AbiFPHZt (ORCPT ); Thu, 16 Jun 2022 03:25:49 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDEBC5C341; Thu, 16 Jun 2022 00:25:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655364348; x=1686900348; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=laArYtF8mBOjJYoElswvAL3XNiFY/jmqVMM9+bukyLs=; b=f3GF5E0j4niAj0pfmjIY+lLyRO3iB7Zm/0ZiUCsYmFNSuKRnOnbgJR8l afcCYd6ZNjHKO91HlX2+ysA7BUXcm0TIqQe3fgWGVhOY7PDvORcvitd+2 VLmiiiOqpKeSSW6hcyQ9L/+nZguc6sI/yjFVR9q2lESuYHmAM3SdTudQ4 x0o7ACHg/IpFiQ9CWZMKdJZg9oSmhVid+uPY3Ljlolqqr9wrM1ZzlwAfl ARf0c1JSdVPWsBXqf+VT/7a5Eihq+GQtu/vd6PqK7aavq0sbvdQv3RlYC Qmb4LLZ6rEK2X2aMbelNpPI1qhXb1AKO3yUsFT2oqLURDoxzA2jv5/VCo g==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="259041571" X-IronPort-AV: E=Sophos;i="5.91,304,1647327600"; d="scan'208";a="259041571" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 00:25:48 -0700 X-IronPort-AV: E=Sophos;i="5.91,304,1647327600"; d="scan'208";a="912045889" Received: from mstokes1-mobl.ger.corp.intel.com (HELO [10.213.198.82]) ([10.213.198.82]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 00:25:44 -0700 Message-ID: Date: Thu, 16 Jun 2022 08:25:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged Content-Language: en-US To: Mauro Carvalho Chehab Cc: Chris Wilson , Fei Yang , =?UTF-8?Q?Micha=c5=82_Winiarski?= , Thomas Hellstrom , Andi Shyti , Daniel Vetter , Daniele Ceraolo Spurio , Dave Airlie , David Airlie , Jani Nikula , John Harrison , Joonas Lahtinen , Lucas De Marchi , Matt Roper , Matthew Auld , Rodrigo Vivi , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com, stable@vger.kernel.org, =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= References: <9d9e663ca8e97becf04e1d4c8cb8a9a1f397a5f1.1655306128.git.mchehab@kernel.org> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc In-Reply-To: <9d9e663ca8e97becf04e1d4c8cb8a9a1f397a5f1.1655306128.git.mchehab@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HK_RANDOM_ENVFROM,HK_RANDOM_FROM, NICE_REPLY_A,RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15/06/2022 16:27, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Skip all further TLB invalidations once the device is wedged and > had been reset, as, on such cases, it can no longer process instructions > on the GPU and the user no longer has access to the TLB's in each engine. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") Are there any real problems fixed or it's just a logical thing to do? Not much harm tagging it as fixes in terms of process since it is tiny but, again, wanting a clear picture. Regards, Tvrtko > Signed-off-by: Chris Wilson > Cc: Fei Yang > Cc: Andi Shyti > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström > Signed-off-by: Mauro Carvalho Chehab > --- > > See [PATCH 0/6] at: https://lore.kernel.org/all/cover.1655306128.git.mchehab@kernel.org/ > > drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 61b7ec5118f9..fb4fd5273ca4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -1226,6 +1226,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > if (I915_SELFTEST_ONLY(gt->awake == -ENODEV)) > return; > > + if (intel_gt_is_wedged(gt)) > + return; > + > if (GRAPHICS_VER(i915) == 12) { > regs = gen12_regs; > num = ARRAY_SIZE(gen12_regs);