Received: by 2002:a6b:fb09:0:0:0:0:0 with SMTP id h9csp1251104iog; Thu, 16 Jun 2022 02:16:00 -0700 (PDT) X-Google-Smtp-Source: AGRyM1svTZXi6y7moh6QxzRct1A2nYhUDp9znzb/LJuUdJiV3S6FE1i4hhun0FljMBdu58LdrbUd X-Received: by 2002:aa7:d586:0:b0:433:5467:8ebf with SMTP id r6-20020aa7d586000000b0043354678ebfmr5134472edq.214.1655370960191; Thu, 16 Jun 2022 02:16:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1655370960; cv=none; d=google.com; s=arc-20160816; b=NEepIgPeS4SODjNeij4W2sEtgW5eCg0qQ0QOuVXmxjK0wa7DcM+sksw6RU2lusIW/L SAAiauvOg/ls+nGO+DaaFqfThdSAccjb5kG3+gp7JZBGL7+dD/aidohXJCW8e9ozPppl pfLtlScE/QJ50PN3Kyf4Bw62iM9b6iygZ8hQbQEpU4TWpdDgGYdY8NQLUVKw4jyQxXnS 0CiaImqFtt5J1shkaprWLaC/QrySYzyewcgogEcO7BZjGxvztiSVvyp6u5lJ8J3d8dST rJXX+IDcNmjCBujQAQZvvyxzDqs39bSxZgss+iYWy+0tcZZq20KNvgazNjZZ2P5dUJUq UN5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=izy7G0Q7eyiWE4CXZRSUEvvAZl4UlL5s+oh9NOxs2Sw=; b=cM1RGltJ0sQHv7H/0EWG54x7z7IywWpMbSKnQXd/K2nuJebDDpJdnJsLHF5TzIsR1z 5RfIHifbuAAj5xB26mhAxqcyk9ErAqULbRjH3HRhaKTLDqpw5u5KsebyzdR42vTDguZx yEiiKc3FJXhHCFN6BOUkCWrCFNmerpQpruYZZlPpk62fEJHPw7TSDEiy0XxqdDkhPLAn 1zEOn8i7ppoOfm6aRhzHikSVI21dStfNkCYm/uUSMdCDlOuN8HrgMq+nK6nTpwlmZ8wk xUdcI1lIyj3JLJCW2lYpHVaelyVEkNB5DN20hct3dM5mDzfPwV/AZyNzpczRVjQHkp7H s0xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=kw2JCD+9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ho9-20020a1709070e8900b00718c003efd7si1165633ejc.988.2022.06.16.02.15.34; Thu, 16 Jun 2022 02:16:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=kw2JCD+9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376547AbiFPIzy (ORCPT + 99 others); Thu, 16 Jun 2022 04:55:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376502AbiFPIzf (ORCPT ); Thu, 16 Jun 2022 04:55:35 -0400 Received: from mail-oa1-x30.google.com (mail-oa1-x30.google.com [IPv6:2001:4860:4864:20::30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 076575DD36 for ; Thu, 16 Jun 2022 01:54:48 -0700 (PDT) Received: by mail-oa1-x30.google.com with SMTP id 586e51a60fabf-1014b2752c1so1109473fac.11 for ; Thu, 16 Jun 2022 01:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=izy7G0Q7eyiWE4CXZRSUEvvAZl4UlL5s+oh9NOxs2Sw=; b=kw2JCD+9bg7YOxTxat/3v8ub8VvvKqI0njMJGF+ad+eadhs27fzl9BFeQv7mXrnXFj 5F0UD7pL4owCnSDf+B/MGtppwdgoOUwI32SrXC9Jnn4hesFB7IpEutH8sv8tadlPdfmz /DTD75UVSaR5k7QhtB/F0kiZBN78lRUe7nShw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=izy7G0Q7eyiWE4CXZRSUEvvAZl4UlL5s+oh9NOxs2Sw=; b=qrCw8TRhZIHeOftHYRMaITSH6qTuvY8zxUCO7RTHdP7k/BHcEXdcU3NKyfuYL9bFlL f5MxSGNonUkw1H8FI6pvLVH9ww3lY1i6zahEvoyzapOyhukVYvavW643UZlsViUWSjgK HDrVyeXfVRfduvM5E/NjeMrpekv1lJntn0IGiIHRtS4P/h4UDnUGi2nQ989gdNcgYZzK /7lB/gkOCpzJxCHwYju1CCsGPxaHJV0CyEzUtyqLbzTSaEata2AuY/OeOBvP6ItJoGc3 gyq4Ep6dXtXVZ4ptexPwu/CiT32ASZDz2+3xujArxR9wOmXiLiX/mPPx9PJjhT/ci7sz FbRQ== X-Gm-Message-State: AJIora9WWCem5NI9b61/m2BUG710N3+rZSF8XQSBHw47prKmePrfGc04 4OQo3MTFX0XboY9TZcXUKyXDzwRz4go9RTKpAd2GRw== X-Received: by 2002:a05:6870:891f:b0:e1:ec98:3c59 with SMTP id i31-20020a056870891f00b000e1ec983c59mr2102642oao.295.1655369687319; Thu, 16 Jun 2022 01:54:47 -0700 (PDT) MIME-Version: 1.0 References: <20220615172129.1314056-1-pmalani@chromium.org> <20220615172129.1314056-5-pmalani@chromium.org> In-Reply-To: From: Prashant Malani Date: Thu, 16 Jun 2022 01:54:36 -0700 Message-ID: Subject: Re: [PATCH v4 4/7] dt-bindings: drm/bridge: anx7625: Add mode-switch support To: Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, bleung@chromium.org, heikki.krogerus@linux.intel.com, =?UTF-8?B?TsOtY29sYXMgRiAuIFIgLiBBIC4gUHJhZG8=?= , Andrzej Hajda , Daniel Vetter , David Airlie , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, Greg Kroah-Hartman , Hsin-Yi Wang , Jernej Skrabec , Jonas Karlman , =?UTF-8?B?Sm9zw6kgRXhww7NzaXRv?= , Krzysztof Kozlowski , Laurent Pinchart , Maxime Ripard , Neil Armstrong , Pin-Yen Lin , Robert Foss , Rob Herring , Sam Ravnborg , Thomas Zimmermann , Xin Ji Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 16, 2022 at 12:42 AM Stephen Boyd wrote: > > Quoting Prashant Malani (2022-06-15 10:20:20) > > > > .../display/bridge/analogix,anx7625.yaml | 64 +++++++++++++++++++ > > 1 file changed, 64 insertions(+) > > Can this file get a link to the product brief[1]? It helps to quickly > find the block diagram. Sure, but I don't really think that should be included in this patch (or series). I'd be happy to submit a separate patch once this series is resolved. > > > > > diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml > > index 35a48515836e..bc6f7644db31 100644 > > --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml > > +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml > > @@ -105,6 +105,34 @@ properties: > > - port@0 > > - port@1 > > > > + switches: > > + type: object > > + description: Set of switches controlling DisplayPort traffic on > > + outgoing RX/TX lanes to Type C ports. > > + additionalProperties: false > > + > > + properties: > > + '#address-cells': > > + const: 1 > > + > > + '#size-cells': > > + const: 0 > > + > > + patternProperties: > > + '^switch@[01]$': > > + $ref: /schemas/usb/typec-switch.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + reg: > > + maxItems: 1 > > + > > + required: > > + - reg > > + > > + required: > > + - switch@0 > > + > > required: > > - compatible > > - reg > > @@ -167,5 +195,41 @@ examples: > > }; > > }; > > }; > > + switches { > > Is "switches" a bus? No. > > > + #address-cells = <1>; > > + #size-cells = <0>; > > + switch@0 { > > + compatible = "typec-switch"; > > Is this compatible matched against a driver that's populated on this > "switches" bus? No. Patch 6/7 has the implementation details on how the anx driver performs the enumeration of switches. > > > + reg = <0>; > > + mode-switch; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + port@0 { > > + reg = <0>; > > + anx_typec0: endpoint { > > + remote-endpoint = <&typec_port0>; > > + }; > > + }; > > + }; > > I was expecting to see these simply be more ports in the existing graph > binding of this device, and then have the 'mode-switch' or > 'orientation-switch' properties be at the same level as the compatible > string "analogix,anx7625". Here's the reasoning, based on looking at the > product brief and the existing binding/implementation. > > Looking at the only existing implementation of this binding upstream in > mt8183-kukui-jacuzzi.dtsi it looks like one of these typec ports is > actually the same physically as the 'anx7625_out' endpoint (reg address > of 1) that is already defined in the binding. It seems that MIPI DSI/DPI > comes in and is output through 2 lanes, SSRX2 and SSTX2 according to the > product brief[1], and that is connected to some eDP panel > ("auo,b116xw03"). Presumably that is the same as anx_typec1 in this > patch? I suspect the USB3.1 input is not connected on this board, and > thus the crosspoint switch is never used, nor the SSRX1/SSTX1 pins. > > The existing binding defines the MIPI DSI/DPI input as port0 and two of > the four lanes of output that is probably by default connected to the > "DisplayPort Transmitter" as port1 because that's how the crosspoint > switch comes out of reset. That leaves the USB3.1 input possibly needing > a port in the ports binding, and the other two lanes of output needing a > port in the ports binding to describe their connection to the downstream > device. And finally information about if the crosspoint switch needs to > be registered with the typec framework to do typec things, which can be > achieved by the presence of the 'mode-switch' property. > > On a board like kukui-jacuzzi these new properties and ports wouldn't be > specified, because what is there is already sufficient. If this chip is > connected to a usb-c-connector then I'd expect to see a connection from > the output ports in the graph binding to the connector node's ports. > There aren't any ports in the usb-c-connector binding though from what I > see. > > I believe there's also one more use case here where USB3.1 or MIPI > DSI/DPI is connected on the input side and this device is used to steer > USB3.1 or DP through the crosspoint switch to either of the two output > pairs. This last scenario means that we have to describe both output > pairs, SSRX1/SSTX1 and SSRX2/SSTX2, as different ports in the binding so > they can be connected to different usb-c-connectors if the hardware > engineer wired the output pins that way. > > TL;DR: Can we add 'mode-switch' as an optional property and two more > ports at address 2 and 3 for the USB3.1 input and the SSRX1/SSTX1 pair > respectively to the existing graph part of this binding? Sorry, but I got lost midway through the preceding explanation. The binding can always add additional ports to each "switch" to accomplish the graph connections you are alluding to (if the driver needs/uses it, which I don't think this one does at present). Adding extra ports to existing ports gets tricky from a mode-switch enumeration perspective (which ports should have the modes switches, which shouldn't? Do you follow the remote end points for each port and see which one is a Type C connector? What if we add an intermediate switch device in the future?) Having a dedicated "switch" binding makes this consistent and easy (port0 will always have the end-point for the switch). While there may be more than 1 valid approach here, I believe the current one is appropriate. > > > + }; > > + switch@1 { > > + compatible = "typec-switch"; > > + reg = <1>; > > + mode-switch; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + port@0 { > > + reg = <0>; > > + anx_typec1: endpoint { > > + remote-endpoint = <&typec_port1>; > > + }; > > + }; > > + }; > > + }; > > + }; > > }; > > [1] https://www.analogix.com/en/system/files/AA-002291-PB-6-ANX7625_ProductBrief.pdf