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Date:   Thu, 16 Jun 2022 09:10:00 -0600
From:   Rob Herring <robh@kernel.org>
To:     Johnson Wang <johnson.wang@mediatek.com>
Cc:     krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
        sboyd@kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org,
        Project_Global_Chrome_Upstream_Group@mediatek.com,
        Edward-JW Yang <edward-jw.yang@mediatek.com>
Subject: Re: [RFC PATCH 1/2] dt-bindings: arm: mediatek: Add new bindings of
 MediaTek frequency hopping
Message-ID: <20220616151000.GA3469769-robh@kernel.org>
References: <20220612135414.3003-1-johnson.wang@mediatek.com>
 <20220612135414.3003-2-johnson.wang@mediatek.com>
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On Sun, Jun 12, 2022 at 09:54:13PM +0800, Johnson Wang wrote:
> This patch adds the new binding documentation for frequency hopping
> and spread spectrum clocking control on MT8186.
> 
> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> ---
>  .../bindings/arm/mediatek/mediatek,fhctl.yaml | 149 ++++++++++++++++++
>  1 file changed, 149 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml
> new file mode 100644
> index 000000000000..9cb04bed9e86
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml
> @@ -0,0 +1,149 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,fhctl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek frequency hopping and spread spectrum clocking control
> +
> +maintainers:
> +  - Edward-JW Yang <edward-jw.yang@mediatek.com>
> +
> +description: |
> +  Frequency hopping control (FHCTL) is a piece of hardware that control
> +  some PLLs to adopt "hopping" mechanism to adjust their frequency.
> +  Spread spectrum clocking (SSC) is another function provided by this hardware.
> +

Are all these settings per board? 

> +properties:
> +  compatible:
> +    const: mediatek,mt8186-fhctl
> +
> +  reg:
> +    maxItems: 2

Need to define what each entry is.

> +
> +patternProperties:
> +  "^map[0-9]$":
> +    type: object

       additionalProperties: false

> +    description:
> +      Represents a group of PLLs controlled by the same domain and method.
> +
> +    properties:
> +      domain:

Custom properties need a vendor prefix.

'domain' is a pretty generic term. 

> +        description: The position of this hardware block in the chip.
> +        $ref: /schemas/types.yaml#/definitions/string-array

You have to define possible values.

> +
> +      method:
> +        description: Determine which method to control this FHCTL hardware.
> +        $ref: /schemas/types.yaml#/definitions/string-array
> +
> +    patternProperties:
> +      "^armpll_(ll|bl)|(cci|main|mm|tvd|m|adsp|mfg|nna|nna2|msdc)pll$":
> +        type: object

           additionalProperties: false

> +        description:
> +          A subnode represents one PLL clock. The properties it contains are
> +          used to determine whether this PLL enable frequency hopping mechanism           and spread spectrum clocking (SSC) control.
> +
> +        properties:
> +          fh-id:
> +            description: The index of the PLL clocks.

index is based on what?

> +            $ref: /schemas/types.yaml#/definitions/uint32
> +
> +          perms:
> +            description:
> +              This is a bit field used to manage the permission of frequency
> +              hopping function and spread spectrum clocking control.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +
> +          ssc-rate:
> +            description: The percentage of the spectrum spreading.

Use '-percent' suffix then.

> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 8
> +
> +        required:
> +          - fh-id
> +          - perms
> +
> +    required:
> +      - domain
> +      - method
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8186-clk.h>
> +    fhctl: fhctl@1000ce00 {
> +        compatible = "mediatek,mt8186-fhctl";
> +        reg = <0x1000ce00 0x200>,
> +              <0x1000c000 0xe00>;
> +        map0 {
> +            domain = "top";
> +            method = "fhctl-ap";
> +
> +            armpll_ll {
> +                fh-id = <0>;
> +                perms = <0x10>;
> +            };
> +
> +            armpll_bl {
> +                fh-id = <1>;
> +                perms = <0x10>;
> +            };
> +
> +            ccipll {
> +                fh-id = <2>;
> +                perms = <0x10>;
> +            };
> +
> +            mainpll {
> +                fh-id = <3>;
> +                perms = <0x1c>;
> +            };
> +
> +            mmpll {
> +                fh-id = <4>;
> +                perms = <0x1c>;
> +            };
> +
> +            tvdpll {
> +                fh-id = <5>;
> +                perms = <0x1c>;
> +            };
> +
> +            mpll {
> +                fh-id = <6>;
> +                perms = <0x10>;
> +            };
> +
> +            adsppll {
> +                fh-id = <7>;
> +                perms = <0x1c>;
> +            };
> +
> +            mfgpll {
> +                fh-id = <8>;
> +                perms = <0x1c>;
> +            };
> +
> +            nnapll {
> +                fh-id = <9>;
> +                perms = <0x1c>;
> +            };
> +
> +            nna2pll {
> +                fh-id = <10>;
> +                perms = <0x1c>;
> +            };
> +
> +            msdcpll {
> +                fh-id = <11>;
> +                perms = <0x1c>;
> +                ssc-rate = <3>;
> +            };
> +        };
> +    };
> -- 
> 2.18.0
> 
>