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Subject: RE: [PATCH 1/2] Define new percpu interface for shared data -- version 3
Date: Wed, 23 May 2007 12:09:56 -0700
Message-ID: <79E93560F4A5FD42BB769DAAF8BEF62A01AA8CF8@scsmsx411.amr.corp.intel.com>
In-Reply-To: <20070523185748.GA4072@localhost.localdomain>
Thread-Topic: [PATCH 1/2] Define new percpu interface for shared data -- version 3
Thread-Index: AcedbDnX+z8wlnV3RbeUWIFyt3JPBgAAKo4A
From: "Yu, Fenghua" <fenghua.yu@intel.com>
To: "Ravikiran G Thirumalai" <kiran@scalex86.org>
Cc: "Andrew Morton" <akpm@linux-foundation.org>,
       "Siddha, Suresh B" <suresh.b.siddha@intel.com>, <clameter@sgi.com>,
       <rmk@arm.linux.org.uk>, <linux-kernel@vger.kernel.org>,
       <schwidefsky@de.ibm.com>, <heiko.carstens@de.ibm.com>
Sender: linux-kernel-owner@vger.kernel.org
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>Has there been any measurable benefit yet due to tail padding?

We don't have data that tail padding actually helps. It all
depends on what data the linker lays out in the cachelines.

As of now we just want to create the infrastructure (so that
more and more people who need it, can use it).

>It would also be interesting to check the wastage/savings on another
large
>cache architecture like S390 (which has a 256 byte cache line)

S390 folks or others might help get the data. I don't have other
machines
on hand.

Thanks.

-Fenghua
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