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a=openpgp-sha256; l=3532; h=from:subject; bh=nfzFDo4vSJe6xj0FTwEJ/U/lIAnr1DaEgJJpcHdVaxw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBirCyqY5ZuFCHuvgCYy0WNIdOndZlC1wP7beVGnIlw N220U86JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCYqwsqgAKCRB33NvayMhJ0ZnOD/ 448XF+A0HBYCR8G5hsszIj07/nBsQTDfXg2FAGCrmM5l6izU4QwCKijtYxwRJcQUAeI+n2/F3bkehj fuLHK4tfiXXGDNIYISm6fuo3b4OjI5uTJ7TK03SF+kRszl2OACvBIkK91dvD30r9Vt3ukMxOkbP7bR qtDueOf0BcQnXOx+cZ6RAY9LbqdEbmKkTYUIQn+CsVYZ6OSUD57FiN2BILOltKIhdoINejZUnvQbso Nrko/HA5QbZ/6nCqXFmxaGERRxuP/wofeRCdvX1aZXamS2/+7jRPAYZ+hUHIF3EwRTHENxT5FdOsXL 04hdOPjYXQEFWRFQrBnzgQs3uwKruSsG0OIB3Xbug4kUmX8HXSERS1ZnSgV5XOlQBRbQJho9y1a6Lc tsqxbFPHI7sfy/FsgaJhgbqoIF5T5kaI/Wf8+8p3luA+0U28tRkwGad6252bLdjyHxtjSYUIbZ9Bcn dmhwxY36KKto7GqwdbHmyeK2r08GCrSmhfkKuJKS68RPkLG/DWbfPOBHU8b72GFJHaI4QKz5qta8n+ 8ddmyn1Nrgk8NkOGKRqnQEgxqO4qhvLbIGyha4tRf5owRWD9UlhPbS0SFR3/KOx92iZAD5a2QxHLNh RnGc64vBzoOuhrJkCdRvoqCVClQB+8YhKSTGFdRVn25OVDMwH/O91clAu6Fw== X-Developer-Key: i=narmstrong@baylibre.com; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on the same Amlogic SoCs. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../display/amlogic,meson-dw-mipi-dsi.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml new file mode 100644 index 000000000000..e057659545a9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-mipi-dsi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller + +maintainers: + - Neil Armstrong + +description: | + The Amlogic Meson Synopsys Designware Integration is composed of + - A Synopsys DesignWare MIPI DSI Host Controller IP + - A TOP control block controlling the Clocks & Resets of the IP + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + enum: + - amlogic,meson-g12a-dw-mipi-dsi + + reg: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + minItems: 2 + items: + - const: pclk + - const: px_clk + - const: meas_clk + + resets: + minItems: 1 + + reset-names: + items: + - const: top + + phys: + minItems: 1 + + phy-names: + items: + - const: dphy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input node to receive pixel data. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + dsi@7000 { + compatible = "amlogic,meson-g12a-dw-mipi-dsi"; + reg = <0x6000 0x400>; + resets = <&reset_top>; + reset-names = "top"; + clocks = <&clk_pclk>, <&clk_px>; + clock-names = "pclk", "px_clk"; + phys = <&mipi_dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VPU VENC Input */ + mipi_dsi_venc_port: port@0 { + reg = <0>; + + mipi_dsi_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + /* DSI Output */ + mipi_dsi_panel_port: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + }; -- 2.25.1