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References: <20220615211415.3111271-1-daolu@rivosinc.com> <6b52cc2c-7bc5-5015-b7a6-4c13bb4789f7@sholland.org>
In-Reply-To: <6b52cc2c-7bc5-5015-b7a6-4c13bb4789f7@sholland.org>
From:   Dao Lu <daolu@rivosinc.com>
Date:   Fri, 17 Jun 2022 09:35:20 -0700
Message-ID: <CAKh7v-QB4+UHjmtmBNQBojx8jB6fDT0WCvjPSPwFU0K_4wqbdg@mail.gmail.com>
Subject: Re: [PATCH v3] arch/riscv: add Zihintpause support
To:     Samuel Holland <samuel@sholland.org>
Cc:     linux-kernel@vger.kernel.org, Heiko Stuebner <heiko@sntech.de>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Atish Patra <atishp@atishpatra.org>,
        Anup Patel <anup@brainfault.org>, Wei Fu <wefu@redhat.com>,
        Niklas Cassel <niklas.cassel@wdc.com>,
        Alexandre Ghiti <alexandre.ghiti@canonical.com>,
        Randy Dunlap <rdunlap@infradead.org>,
        Qinglin Pan <panqinglin2020@iscas.ac.cn>,
        Rob Herring <robh@kernel.org>,
        Tsukasa OI <research_trasio@irq.a4lg.com>,
        Yury Norov <yury.norov@gmail.com>,
        "open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>
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Will look at rebasing to use the unified static key mechanism for
the next version.

Regards,
Dao

On Thu, Jun 16, 2022 at 8:49 PM Samuel Holland <samuel@sholland.org> wrote:
>
> On 6/15/22 4:14 PM, Dao Lu wrote:
> > Implement support for the ZiHintPause extension.
> >
> > The PAUSE instruction is a HINT that indicates the current hart=E2=80=
=99s rate
> > of instruction retirement should be temporarily reduced or paused.
> >
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> > Tested-by: Heiko Stuebner <heiko@sntech.de>
> > Signed-off-by: Dao Lu <daolu@rivosinc.com>
> > ---
> >
> > v1 -> v2:
> >  Remove the usage of static branch, use PAUSE if toolchain supports it
> > v2 -> v3:
> >  Added the static branch back, cpu_relax() behavior is unchanged if eit=
her the
> > system or the toolchain does not support ZiHintPause
> > ---
> >  arch/riscv/Makefile                     |  4 ++++
> >  arch/riscv/include/asm/hwcap.h          |  1 +
> >  arch/riscv/include/asm/vdso/processor.h | 19 ++++++++++++++++---
> >  arch/riscv/kernel/cpu.c                 |  1 +
> >  arch/riscv/kernel/cpufeature.c          |  8 ++++++++
> >  5 files changed, 30 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > index 34cf8a598617..6ddacc6f44b9 100644
> > --- a/arch/riscv/Makefile
> > +++ b/arch/riscv/Makefile
> > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C)  :=3D $(riscv-marc=
h-y)c
> >  toolchain-need-zicsr-zifencei :=3D $(call cc-option-yn, -march=3D$(ris=
cv-march-y)_zicsr_zifencei)
> >  riscv-march-$(toolchain-need-zicsr-zifencei) :=3D $(riscv-march-y)_zic=
sr_zifencei
> >
> > +# Check if the toolchain supports Zihintpause extension
> > +toolchain-supports-zihintpause :=3D $(call cc-option-yn, -march=3D$(ri=
scv-march-y)_zihintpause)
> > +riscv-march-$(toolchain-supports-zihintpause) :=3D $(riscv-march-y)_zi=
hintpause
> > +
> >  KBUILD_CFLAGS +=3D -march=3D$(subst fd,,$(riscv-march-y))
> >  KBUILD_AFLAGS +=3D -march=3D$(riscv-march-y)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hw=
cap.h
> > index 4e2486881840..f24f4f8c9144 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -53,6 +53,7 @@ extern unsigned long elf_hwcap;
> >  enum riscv_isa_ext_id {
> >       RISCV_ISA_EXT_SSCOFPMF =3D RISCV_ISA_EXT_BASE,
> >       RISCV_ISA_EXT_SVPBMT,
> > +     RISCV_ISA_EXT_ZIHINTPAUSE,
> >       RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX,
> >  };
> >
> > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/inclu=
de/asm/vdso/processor.h
> > index 134388cbaaa1..314ec17c40d8 100644
> > --- a/arch/riscv/include/asm/vdso/processor.h
> > +++ b/arch/riscv/include/asm/vdso/processor.h
> > @@ -4,15 +4,28 @@
> >
> >  #ifndef __ASSEMBLY__
> >
> > +#include <linux/jump_label.h>
> >  #include <asm/barrier.h>
> > +#include <asm/hwcap.h>
> >
> > +extern struct static_key_false riscv_pause_available;
> >  static inline void cpu_relax(void)
> >  {
> > +     if (!static_branch_likely(&riscv_pause_available)) {
> >  #ifdef __riscv_muldiv
> > -     int dummy;
> > -     /* In lieu of a halt instruction, induce a long-latency stall. */
> > -     __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy));
> > +             int dummy;
> > +             /* In lieu of a halt instruction, induce a long-latency s=
tall. */
> > +             __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy)=
);
> >  #endif
> > +#ifdef __riscv_zihintpause
> > +     } else {
> > +             /*
> > +              * Reduce instruction retirement.
> > +              * This assumes the PC changes.
> > +              */
> > +             __asm__ __volatile__ ("pause");
> > +#endif
> > +     }
> >       barrier();
> >  }
> >
> > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> > index fba9e9f46a8c..a123e92b14dd 100644
> > --- a/arch/riscv/kernel/cpu.c
> > +++ b/arch/riscv/kernel/cpu.c
> > @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node)
> >  static struct riscv_isa_ext_data isa_ext_arr[] =3D {
> >       __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> >       __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > +     __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> >       __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
> >  };
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeat=
ure.c
> > index a6f62a6d1edd..78c284c487e8 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -30,6 +30,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) _=
_read_mostly;
> >  #ifdef CONFIG_FPU
> >  __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
> >  #endif
> > +DEFINE_STATIC_KEY_FALSE(riscv_pause_available);
> > +EXPORT_SYMBOL_GPL(riscv_pause_available);
>
> This patch should probably be rebased to use the unified static key
> mechanism[1], since that patch has now been merged.
>
> Regards,
> Samuel
>
> [1]: https://lore.kernel.org/linux-riscv/20220522153543.2656-2-jszhang@ke=
rnel.org/