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From:   "Gogada, Bharat Kumar" <bharat.kumar.gogada@amd.com>
To:     Bjorn Helgaas <helgaas@kernel.org>,
        Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        "michals@xilinx.com" <michals@xilinx.com>,
        "robh@kernel.org" <robh@kernel.org>
Subject: RE: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port
Thread-Topic: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port
Thread-Index: AQHYgX7ZyqV524NBuEaYF92mjmwPz61SW38AgAIZedA=
Date:   Sat, 18 Jun 2022 02:35:54 +0000
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References: <20220616124429.12917-1-bharat.kumar.gogada@xilinx.com>
 <20220616183108.GA1101056@bhelgaas>
In-Reply-To: <20220616183108.GA1101056@bhelgaas>
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> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
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>=20
>=20
> On Thu, Jun 16, 2022 at 06:14:27PM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root Port
> > functioning at Gen5 speed.
> >
> > Xilinx Versal CPM5 has few changes with existing CPM block.
> > - CPM5 has dedicated register space for control and status registers.
> > - CPM5 legacy interrupt handling needs additonal register bit
> >   to enable and handle legacy interrupts.
> >
> > Changes in v5:
> > - Added of_device_get_match_data to identify CPM version.
> >
> >
> > Bharat Kumar Gogada (2):
> >   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
> >   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
> >
> >  .../bindings/pci/xilinx-versal-cpm.yaml       | 48 ++++++++++++--
> >  drivers/pci/controller/pcie-xilinx-cpm.c      | 62 ++++++++++++++++++-
> >  2 files changed, 103 insertions(+), 7 deletions(-)
>=20
> Weren't you going to include a MAINTAINERS update here?
>=20
> https://lore.kernel.org/r/BY5PR02MB6947C5B34801AD5F289127ABA5A69@B
> Y5PR02MB6947.namprd02.prod.outlook.com
>=20
> Maybe I missed it?
>=20
HI Bjorn,=20

I planned to send it separately. Will send this soon.

Regards,
Bharat