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Message-ID: <cdead652-cbd6-90e4-dab8-9cb18f71a624@bytedance.com>
Date:   Mon, 20 Jun 2022 18:02:32 +0800
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Subject: Re: [External] [PATCH v9 9/9] KVM: VMX: enable IPI virtualization
To:     Zeng Guang <guang.zeng@intel.com>
Cc:     Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <seanjc@google.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>, kvm@vger.kernel.org,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Kan Liang <kan.liang@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Kim Phillips <kim.phillips@amd.com>,
        Jarkko Sakkinen <jarkko@kernel.org>,
        Jethro Beekman <jethro@fortanix.com>,
        Kai Huang <kai.huang@intel.com>, x86@kernel.org,
        linux-kernel@vger.kernel.org, Robert Hu <robert.hu@intel.com>,
        Gao Chao <chao.gao@intel.com>, zhouyibo@bytedance.com
References: <20220419154510.11938-1-guang.zeng@intel.com>
From:   Shenming Lu <lushenming@bytedance.com>
In-Reply-To: <20220419154510.11938-1-guang.zeng@intel.com>
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On 19/04/2022 23:45, Zeng Guang wrote:
> From: Chao Gao <chao.gao@intel.com>
> 
> With IPI virtualization enabled, the processor emulates writes to
> APIC registers that would send IPIs. The processor sets the bit
> corresponding to the vector in target vCPU's PIR and may send a
> notification (IPI) specified by NDST and NV fields in target vCPU's
> Posted-Interrupt Descriptor (PID). It is similar to what IOMMU
> engine does when dealing with posted interrupt from devices.
> 

...


> @@ -3872,6 +3875,8 @@ static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
>   		vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
>   		vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
>   		vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
> +		if (enable_ipiv)
> +			vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW);
>   	}
>   }
>   
> @@ -4195,14 +4200,19 @@ static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
>   
>   	pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
>   
> -	if (kvm_vcpu_apicv_active(vcpu))
> +	if (kvm_vcpu_apicv_active(vcpu)) {
>   		secondary_exec_controls_setbit(vmx,
>   					       SECONDARY_EXEC_APIC_REGISTER_VIRT |
>   					       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
> -	else
> +		if (enable_ipiv)
> +			tertiary_exec_controls_setbit(vmx, TERTIARY_EXEC_IPI_VIRT);
> +	} else {
>   		secondary_exec_controls_clearbit(vmx,
>   						 SECONDARY_EXEC_APIC_REGISTER_VIRT |
>   						 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
> +		if (enable_ipiv)
> +			tertiary_exec_controls_clearbit(vmx, TERTIARY_EXEC_IPI_VIRT);
> +	}
>   
>   	vmx_update_msr_bitmap_x2apic(vcpu);
>   }

Hi, just a small question here:

It seems that we clear the TERTIARY_EXEC_IPI_VIRT bit before enabling
interception for APIC_ICR when deactivating APICv on some reason.
Is there any problem with this sequence?

Thanks,
shenming