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From:   Tomer Maimon <tmaimon77@gmail.com>
Date:   Mon, 20 Jun 2022 15:48:10 +0300
Message-ID: <CAP6Zq1jT3fbbRzDhriPT7JVYsrAOVGa4ukL_3yh_=wj-4f6zyA@mail.gmail.com>
Subject: Re: [PATCH v3 06/18] clk: npcm8xx: add clock controller
To:     Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Cc:     Arnd Bergmann <arnd@arndb.de>,
        Avi Fishman <avifishman70@gmail.com>,
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Precedence: bulk

Hi Christophe,

Thanks for your comments.

On Sun, 19 Jun 2022 at 20:14, Christophe JAILLET
<christophe.jaillet@wanadoo.fr> wrote:
>
> Le 19/06/2022 =C3=A0 17:12, Tomer Maimon a =C3=A9crit :
> > Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller which
> > generates and supplies clocks to all modules within the BMC.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77-Re5JQEeQqe8AvxtiuMwx3w@public.gm=
ane.org>
> > ---
> >   drivers/clk/Kconfig       |   6 +
> >   drivers/clk/Makefile      |   1 +
> >   drivers/clk/clk-npcm8xx.c | 760 +++++++++++++++++++++++++++++++++++++=
+
> >   3 files changed, 767 insertions(+)
> >   create mode 100644 drivers/clk/clk-npcm8xx.c
> >
>
> [...]
>
> Hi, below a few comments related to error handling and possible
> dev_err_probe() usage to savec a few LoC.
>
> CJ
>
> > +static struct clk_hw *
> > +npcm8xx_clk_register_pll(struct device *dev, void __iomem *pllcon,
> > +                      const char *name, const char *parent_name,
> > +                      unsigned long flags)
> > +{
> > +     struct npcm8xx_clk_pll *pll;
> > +     struct clk_init_data init;
> > +     struct clk_hw *hw;
> > +     int ret;
> > +
> > +     pll =3D kzalloc(sizeof(*pll), GFP_KERNEL);
> > +     if (!pll)
> > +             return ERR_PTR(-ENOMEM);
> > +
> > +     pr_debug("%s reg, name=3D%s, p=3D%s\n", __func__, name, parent_na=
me);
> > +
> > +     init.name =3D name;
> > +     init.ops =3D &npcm8xx_clk_pll_ops;
> > +     init.parent_names =3D &parent_name;
> > +     init.num_parents =3D 1;
> > +     init.flags =3D flags;
> > +
> > +     pll->pllcon =3D pllcon;
> > +     pll->hw.init =3D &init;
> > +
> > +     hw =3D &pll->hw;
> > +
> > +     ret =3D devm_clk_hw_register(dev, hw);
> > +     if (ret) {
> > +             kfree(pll);
>
> Hi,
>
> there is no other kfree(() in this patch. It is handled by the framework
> once the clk is registered or should there be another kfree() somewhere
> or should pll be devm_alloc()'ed?
Could use the devm_kzalloc but the hw is sent to the devm function and
not the pll struct.
>
>
> > +             return ERR_PTR(ret);
> > +     }
> > +
> > +     return hw;
> > +}
> > +
>
> [...]
>
> > +static int npcm8xx_clk_probe(struct platform_device *pdev)
> > +{
> > +     struct clk_hw_onecell_data *npcm8xx_clk_data;
> > +     struct device *dev =3D &pdev->dev;
> > +     void __iomem *clk_base;
> > +     struct clk_hw *hw;
> > +     int i;
> > +
> > +     npcm8xx_clk_data =3D devm_kzalloc(dev, struct_size(npcm8xx_clk_da=
ta, hws,
> > +                                                      NPCM8XX_NUM_CLOC=
KS),
> > +                                     GFP_KERNEL);
> > +     if (!npcm8xx_clk_data)
> > +             return -ENOMEM;
> > +
> > +     clk_base =3D devm_platform_ioremap_resource(pdev, 0);
> > +     if (IS_ERR(clk_base))
> > +             return PTR_ERR(clk_base);
> > +
> > +     npcm8xx_clk_data->num =3D NPCM8XX_NUM_CLOCKS;
> > +
> > +     for (i =3D 0; i < NPCM8XX_NUM_CLOCKS; i++)
> > +             npcm8xx_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER);
> > +
> > +     /* Reference 25MHz clock */
> > +     hw =3D clk_hw_register_fixed_rate(dev, "refclk", NULL, 0, NPCM8XX=
_REF_CLK);
>
> Other resoruces are managed, but not this one.
> Is it on purpose?
This is the fixed clock - the SoC Reference clock, what do you mean by
not managed?
> Is an error handling path needed or a devm_add_action_or_reset()?
>
> > +     if (IS_ERR(hw))
> > +             return PTR_ERR(hw);
> > +     npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK] =3D hw;
> > +
> > +     /* Register plls */
> > +     for (i =3D 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> > +             const struct npcm8xx_clk_pll_data *pll_data =3D &npcm8xx_=
plls[i];
> > +
> > +             hw =3D npcm8xx_clk_register_pll(dev, clk_base + pll_data-=
>reg,
> > +                                           pll_data->name,
> > +                                           pll_data->parent_name,
> > +                                           pll_data->flags);
> > +             if (IS_ERR(hw)) {
> > +                     dev_err(dev, "npcm8xx_clk: Can't register pll\n")=
;
> > +                     return PTR_ERR(hw);
> > +             }
> > +
> > +             if (pll_data->onecell_idx >=3D 0)
> > +                     npcm8xx_clk_data->hws[pll_data->onecell_idx] =3D =
hw;
> > +     }
> > +
> > +     /* Register fixed dividers */
> > +     hw =3D devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL1_=
DIV2,
> > +                                            NPCM8XX_CLK_S_PLL1, 0, 1, =
2);
> > +     if (IS_ERR(hw)) {
> > +             dev_err(dev, "npcm8xx_clk: Can't register fixed div\n");
> > +             return PTR_ERR(hw);
>
> return dev_err_probe()?
it will save online but still enter to a bigger function, I am not
sure that the error will be EPROBE_DEFER, and we have returned the
error in the code.
>
> > +     }
> > +
> > +     hw =3D devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL2_=
DIV2,
> > +                                            NPCM8XX_CLK_S_PLL2, 0, 1, =
2);
> > +     if (IS_ERR(hw)) {
> > +             dev_err(dev, "npcm8xx_clk: Can't register pll div2\n");
> > +             return PTR_ERR(hw);
>
> Same here and in other calls below.
>
> > +     }
> > +
> > +     hw =3D devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PRE_C=
LK,
> > +                                            NPCM8XX_CLK_S_CPU_MUX, 0, =
1, 2);
> > +     if (IS_ERR(hw)) {
> > +             dev_err(dev, "npcm8xx_clk: Can't register ckclk div2\n");
> > +             return PTR_ERR(hw);
> > +     }
> > +
> > +     hw =3D devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_AXI,
> > +                                            NPCM8XX_CLK_S_TH, 0, 1, 2)=
;
> > +     if (IS_ERR(hw)) {
> > +             dev_err(dev, "npcm8xx_clk: Can't register axi div2\n");
> > +             return PTR_ERR(hw);
> > +     }
> > +
> > +     hw =3D devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_ATB,
> > +                                            NPCM8XX_CLK_S_AXI, 0, 1, 2=
);
> > +     if (IS_ERR(hw)) {
> > +             dev_err(dev, "npcm8xx_clk: Can't register atb div2\n");
> > +             return PTR_ERR(hw);
> > +     }
> > +
> > +     /* Register muxes */
> > +     for (i =3D 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> > +             const struct npcm8xx_clk_mux_data *mux_data =3D &npcm8xx_=
muxes[i];
> > +
> > +             hw =3D clk_hw_register_mux_table(dev, mux_data->name,
> > +                                            mux_data->parent_names,
> > +                                            mux_data->num_parents,
> > +                                            mux_data->flags,
> > +                                            clk_base + NPCM8XX_CLKSEL,
> > +                                            mux_data->shift,
> > +                                            mux_data->mask, 0,
> > +                                            mux_data->table,
> > +                                            &npcm8xx_clk_lock);
> > +
> Same here. Error handling?
what do you mean?
>
> > +             if (IS_ERR(hw)) {
> > +                     dev_err(dev, "npcm8xx_clk: Can't register mux\n")=
;
> > +                     return PTR_ERR(hw);
> > +             }
> > +
> > +             if (mux_data->onecell_idx >=3D 0)
> > +                     npcm8xx_clk_data->hws[mux_data->onecell_idx] =3D =
hw;
> > +     }
> > +
> > +     /* Register clock dividers specified in npcm8xx_divs */
> > +     for (i =3D 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> > +             const struct npcm8xx_clk_div_data *div_data =3D &npcm8xx_=
divs[i];
> > +
> > +             hw =3D clk_hw_register_divider(dev, div_data->name,
> > +                                          div_data->parent_name,
> > +                                          div_data->flags,
> > +                                          clk_base + div_data->reg,
> > +                                          div_data->shift, div_data->w=
idth,
> > +                                          div_data->clk_divider_flags,
> > +                                          &npcm8xx_clk_lock);
>
> devm_clk_hw_register_divider()?
Will do.
>
> > +             if (IS_ERR(hw)) {
> > +                     dev_err(dev, "npcm8xx_clk: Can't register div tab=
le\n");
> > +                     return PTR_ERR(hw);
> > +             }
> > +
> > +             if (div_data->onecell_idx >=3D 0)
> > +                     npcm8xx_clk_data->hws[div_data->onecell_idx] =3D =
hw;
> > +     }
> > +
> > +     return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> > +                                        npcm8xx_clk_data);
> > +}
> > +
> > +static const struct of_device_id npcm8xx_clk_dt_ids[] =3D {
> > +     { .compatible =3D "nuvoton,npcm845-clk", },
> > +     { }
> > +};
> > +MODULE_DEVICE_TABLE(of, npcm8xx_clk_dt_ids);
> > +
> > +static struct platform_driver npcm8xx_clk_driver =3D {
> > +     .probe  =3D npcm8xx_clk_probe,
> > +     .driver =3D {
> > +             .name =3D "npcm8xx_clk",
> > +             .of_match_table =3D npcm8xx_clk_dt_ids,
> > +     },
> > +};
> > +
> > +static int __init npcm8xx_clk_driver_init(void)
> > +{
> > +     return platform_driver_register(&npcm8xx_clk_driver);
> > +}
> > +arch_initcall(npcm8xx_clk_driver_init);
> > +
>

Best regards,

Tomer