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Peter Anvin" , Kim Phillips , Jarkko Sakkinen , Jethro Beekman , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, Robert Hu , zhouyibo@bytedance.com References: <20220419154510.11938-1-guang.zeng@intel.com> <20220620105957.GA9496@gao-cwp> From: Shenming Lu In-Reply-To: <20220620105957.GA9496@gao-cwp> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/06/2022 19:00, Chao Gao wrote: > On Mon, Jun 20, 2022 at 06:02:32PM +0800, Shenming Lu wrote: >>> + if (enable_ipiv) >>> + tertiary_exec_controls_clearbit(vmx, TERTIARY_EXEC_IPI_VIRT); >>> + } >>> vmx_update_msr_bitmap_x2apic(vcpu); >>> } >> >> Hi, just a small question here: >> >> It seems that we clear the TERTIARY_EXEC_IPI_VIRT bit before enabling >> interception for APIC_ICR when deactivating APICv on some reason. >> Is there any problem with this sequence? > > Both are done before the next vCPU entry. As long as no guest code can > run between them (APICv setting takes effect in guest), this sequence > shouldn't have any problem. OK. Thanks for reply, Shenmimg