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References: <20220621111818.447452-1-robimarko@gmail.com> <20220621111818.447452-2-robimarko@gmail.com>
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From:   Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date:   Tue, 21 Jun 2022 20:26:00 +0300
Message-ID: <CAA8EJposq4796b33jkovDDQdzQsrp733kN5tQYAhFow4G8hvow@mail.gmail.com>
Subject: Re: [PATCH v2 2/2] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support
To:     Robert Marko <robimarko@gmail.com>
Cc:     agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com,
        vkoul@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org,
        linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
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On Tue, 21 Jun 2022 at 14:18, Robert Marko <robimarko@gmail.com> wrote:
>
> IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3.
> Gen2 one is already supported, so add the support for the Gen3 one.
> It uses the same register layout as IPQ6018.
>
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
> Changes in v2:
> * Rebase onto next-20220621 to apply on the refactored driver
> * Remove non existant has_phy_com_ctrl and has_lane_rst
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 171 ++++++++++++++++++++++-
>  1 file changed, 169 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index b2cd0cf965d8..b4836417b2c0 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

[skipped]

> @@ -2121,8 +2277,16 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
>
>         init.ops = &clk_fixed_rate_ops;
>
> -       /* controllers using QMP phys use 125MHz pipe clock interface */
> -       fixed->fixed_rate = 125000000;
> +       /*
> +        * Controllers using QMP PHY-s use 125MHz pipe clock interface
> +        * unless other frequency is specified in the DTS.
> +        */
> +       ret = of_property_read_u32(np, "clock-output-rate", &rate);

The clock-output-rate is a new property, which doesn't exist yet. If
the rate is peculiar to your platform/PHY, I'd suggest adding a field
to the qmp configuration instead.

> +       if (ret)
> +               fixed->fixed_rate = 125000000;
> +       else
> +               fixed->fixed_rate = rate;
> +
>         fixed->hw.init = &init;
>
>         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
> @@ -2255,6 +2419,9 @@ static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = {
>         }, {
>                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
>                 .data = &ipq8074_pciephy_cfg,
> +       }, {
> +               .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
> +               .data = &ipq8074_pciephy_gen3_cfg,
>         }, {
>                 .compatible = "qcom,ipq6018-qmp-pcie-phy",
>                 .data = &ipq6018_pciephy_cfg,
> --
> 2.36.1
>


-- 
With best wishes
Dmitry