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Date:   Tue, 21 Jun 2022 15:38:29 -0700
From:   Davidlohr Bueso <dave@stgolabs.net>
To:     Dan Williams <dan.j.williams@intel.com>
Cc:     linux-cxl@vger.kernel.org, alison.schofield@intel.com,
        bwidawsk@kernel.org, ira.weiny@intel.com, vishal.l.verma@intel.com,
        a.manzanares@samsung.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] cxl/acpi: Verify CHBS consistency
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References: <20220621201259.1547474-1-dave@stgolabs.net>
 <62b230881a77_8920729456@dwillia2-xfh.notmuch>
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On Tue, 21 Jun 2022, Dan Williams wrote:

>For cxl_port objects this happens "for free" as a side effect of the:
>
>        crb = devm_cxl_iomap_block(dev, port->component_reg_phys,
>                                   CXL_COMPONENT_REG_BLOCK_SIZE);
>
>...call in devm_cxl_setup_hdm(), where it tries to exclusively claim the
>component register block for that cxl_port driver instance.

Fair enough, I had noticed this.

>
>I.e. if the CHBS provides overlapping / duplicated ranges the failure is
>localized to the cxl_port_probe() event for that port, and can be
>debugged further by disabling one of the conflicts.

Ok. Although imo it does make sense for failing directly in the cxl_acpi
driver at an early stage instead of bogusly passing it down the hierarchy.

So is a v2 still worth it without this check?

Thanks,
Davidlohr