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From:   Peter Korsgaard <peter@korsgaard.com>
To:     Nava kishore Manne <nava.manne@xilinx.com>
Cc:     <michal.simek@xilinx.com>, <hao.wu@intel.com>, <trix@redhat.com>,
        <mdf@kernel.org>, <yilun.xu@intel.com>,
        <gregkh@linuxfoundation.org>, <ronak.jain@xilinx.com>,
        <rajan.vaja@xilinx.com>, <abhyuday.godhasara@xilinx.com>,
        <piyush.mehta@xilinx.com>, <harsha.harsha@xilinx.com>,
        <lakshmi.sai.krishna.potthuri@xilinx.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <linux-fpga@vger.kernel.org>,
        <git@xilinx.com>
Subject: Re: [PATCH v2 3/3] fpga: zynqmp-fpga: Adds status interface
References: <20220621092833.1057408-1-nava.manne@xilinx.com>
        <20220621092833.1057408-4-nava.manne@xilinx.com>
Date:   Wed, 22 Jun 2022 14:16:47 +0200
In-Reply-To: <20220621092833.1057408-4-nava.manne@xilinx.com> (Nava kishore
        Manne's message of "Tue, 21 Jun 2022 14:58:33 +0530")
Message-ID: <87edzg51w0.fsf@dell.be.48ers.dk>
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>>>>> "Nava" == Nava kishore Manne <nava.manne@xilinx.com> writes:

 > Adds status interface for zynqmp-fpga, It's a read only
 > interface which allows the user to get the PL status.

 > Usage:
 > To read the PL configuration status
 >         cat /sys/class/fpga_manager/<fpga>/status

 > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
 > ---
 > Changes for v2:
 >               - Updated status messages handling logic as suggested by Xu Yilun.

 >  drivers/fpga/zynqmp-fpga.c | 53 ++++++++++++++++++++++++++++++++++++++
 >  1 file changed, 53 insertions(+)

 > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
 > index c60f20949c47..e194bba91d3f 100644
 > --- a/drivers/fpga/zynqmp-fpga.c
 > +++ b/drivers/fpga/zynqmp-fpga.c
 > @@ -14,6 +14,19 @@
 
 >  /* Constant Definitions */
 >  #define IXR_FPGA_DONE_MASK	BIT(3)
 > +#define READ_DMA_SIZE		256U
 > +
 > +/* Error Register */
 > +#define IXR_FPGA_ERR_CRC_ERR		BIT(0)
 > +#define IXR_FPGA_ERR_SECURITY_ERR	BIT(16)
 > +
 > +/* Signal Status Register. For details refer ug570 */
 > +#define IXR_FPGA_END_OF_STARTUP		BIT(4)
 > +#define IXR_FPGA_GST_CFG_B		BIT(5)
 > +#define IXR_FPGA_INIT_B_INTERNAL	BIT(11)
 > +#define IXR_FPGA_DONE_INTERNAL_SIGNAL	BIT(13)
 > +
 > +#define IXR_FPGA_CONFIG_STAT_OFFSET	7U
 
 >  /**
 >   * struct zynqmp_fpga_priv - Private data structure
 > @@ -77,8 +90,48 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
 >  	return FPGA_MGR_STATE_UNKNOWN;
 >  }
 
 > +static ssize_t zynqmp_fpga_ops_status(struct fpga_manager *mgr, char *buf)
 > +{
 > +	unsigned int *kbuf, reg_val;
 > +	dma_addr_t dma_addr;
 > +	ssize_t len = 0;
 > +	int ret;
 > +
 > +	kbuf = dma_alloc_coherent(mgr->dev.parent, READ_DMA_SIZE,
 > +				  &dma_addr, GFP_KERNEL);
 > +	if (!kbuf)
 > +		return -ENOMEM;

What is kbuf used for? You don't seem to ever access it?

-- 
Bye, Peter Korsgaard