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[192.222.136.102]) by smtp.gmail.com with ESMTPSA id m22-20020a05620a291600b006a370031c3esm17833638qkp.106.2022.06.22.12.39.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 12:39:37 -0700 (PDT) Message-ID: <9178e19f5c0e141772b61b759abaa0d176f902b6.camel@ndufresne.ca> Subject: Re: DMA-buf and uncached system memory From: Nicolas Dufresne To: Daniel Vetter , Christian =?ISO-8859-1?Q?K=F6nig?= Cc: linux-media , dri-devel , linaro-mm-sig@lists.linaro.org, lkml , Sumit Semwal , "Sharma, Shashank" Date: Wed, 22 Jun 2022 15:39:36 -0400 In-Reply-To: References: <91ff0bbb-ea3a-2663-3453-dea96ccd6dd8@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.2 (3.44.2-1.fc36) MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le mardi 16 f=C3=A9vrier 2021 =C3=A0 10:25 +0100, Daniel Vetter a =C3=A9cri= t=C2=A0: > So I think if AMD also guarantees to drop clean cachelines just do the > same thing we do right now for intel integrated + discrete amd, but in > reserve. It's fragile, but it does work. Sorry to disrupt, but if you pass V4L2 vmalloc data to Intel display driver= , you also get nice dirt on the screen. If you have a UVC webcam that produces a = pixel format compatible with your display, you can reproduce the issue quite easi= ly with: gst-launch-1.0 v4l2src device=3D/dev/video0 ! kmssink p.s. some frame-rate are less likely to exhibit the issue, make sure you cr= eate movement to see it. The only solution I could think of (not implemented) was to detect in the attach() call what the importers can do (with dev->coherent_dma_mask if I recall), and otherwise flush the cache immediately and start flushing the c= ache from now on signalling it for DQBUF (in vb2 workqueue or dqbuf ioctl, I don= 't have an idea yet). I bet this idea is inapplicable to were you have fences,= we don't have that in v4l2. This idea was hinted by Robert Becket (now in CC), but perhaps I picked it = up wrong, explaining it wrong, etc. I'm no expert, just noticed there wasn't r= eally a good plan for that, so one needs to make one up. I'm not aware oh an impo= rter could know how the memory was allocated by the exporter, and worst, how an importer could figure-out that the export is going to produce buffer with h= ot CPU cache (UVC driver does memcpy from USB chunks of variable size to produ= ce a fixed size image). Nicolas