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Date:   Thu, 23 Jun 2022 11:46:32 +0200
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Subject: Re: DMA-buf and uncached system memory
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To:     Lucas Stach <l.stach@pengutronix.de>,
        Pekka Paalanen <ppaalanen@gmail.com>
Cc:     "Sharma, Shashank" <Shashank.Sharma@amd.com>,
        lkml <linux-kernel@vger.kernel.org>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        Nicolas Dufresne <nicolas@ndufresne.ca>,
        linaro-mm-sig@lists.linaro.org,
        Sumit Semwal <sumit.semwal@linaro.org>,
        linux-media <linux-media@vger.kernel.org>
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From:   =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>
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Am 23.06.22 um 11:33 schrieb Lucas Stach:
> [SNIP]
>>>>> In the DMA API keeping things mapped is also a valid use-case, but then
>>>>> you need to do explicit domain transfers via the dma_sync_* family,
>>>>> which DMA-buf has not inherited. Again those sync are no-ops on cache
>>>>> coherent architectures, but do any necessary cache maintenance on non
>>>>> coherent arches.
>>>> Correct, yes. Coherency is mandatory for DMA-buf, you can't use
>>>> dma_sync_* on it when you are the importer.
>>>>
>>>> The exporter could of course make use of that because he is the owner of
>>>> the buffer.
>>> In the example given here with UVC video, you don't know that the
>>> buffer will be exported and needs to be coherent without
>>> synchronization points, due to the mapping cache at the DRM side. So
>>> V4L2 naturally allocates the buffers from CPU cached memory. If the
>>> expectation is that those buffers are device coherent without relying
>>> on the map/unmap_attachment calls, then V4L2 needs to always
>>> synchronize caches on DQBUF when the  buffer is allocated from CPU
>>> cached memory and a single DMA-buf attachment exists. And while writing
>>> this I realize that this is probably exactly what V4L2 should do...
>> No, the expectation is that the importer can deal with whatever the
>> exporter provides.
>>
>> If the importer can't access the DMA-buf coherently it's his job to
>> handle that gracefully.
> How does the importer know that the memory behind the DMA-buf is in CPU
> cached memory?
>
> If you now tell me that an importer always needs to assume this and
> reject the import if it can't do snooping, then any DMA-buf usage on
> most ARM SoCs is currently invalid usage.

Yes, exactly that. I've pointed out a couple of times now that a lot of 
ARM SoCs don't implement that the way we need it.

We already had tons of bug reports because somebody attached a random 
PCI root complex to an ARM SoC and expected it to work with for example 
an AMD GPU.

Non-cache coherent applications are currently not really supported by 
the DMA-buf framework in any way.

> On most of the multimedia
> targeted ARM SoCs being unable to snoop the cache is the norm, not an
> exception.
>
>> See for example on AMD/Intel hardware most of the engines can perfectly
>> deal with cache coherent memory accesses. Only the display engines can't.
>>
>> So on import time we can't even say if the access can be coherent and
>> snoop the CPU cache or not because we don't know how the imported
>> DMA-buf will be used later on.
>>
> So for those mixed use cases, wouldn't it help to have something
> similar to the dma_sync in the DMA-buf API, so your scanout usage can
> tell the exporter that it's going to do non-snoop access and any dirty
> cache lines must be cleaned? Signaling this to the exporter would allow
> to skip the cache maintenance if the buffer is in CPU uncached memory,
> which again is a default case for the ARM SoC world.

Well for the AMD and Intel use cases we at least have the opportunity to 
signal cache flushing, but I'm not sure if that counts for everybody.

What we would rather do for those use cases is an indicator on the 
DMA-buf if the underlying backing store is CPU cached or not. The 
importer can then cleanly reject the use cases where it can't support 
CPU cache snooping.

This then results in the normal fallback paths which we have anyway for 
those use cases because DMA-buf sharing is not always possible.

Regards,
Christian.

>
> Regards,
> Lucas
>