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From:   David Laight <David.Laight@ACULAB.COM>
To:     'George Cherian' <george.cherian@marvell.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "sgoutham@marvell.com" <sgoutham@marvell.com>,
        "tglx@linutronix.de" <tglx@linutronix.de>
Subject: RE: [PATCH] genirq: Increase the number of interrupters
Thread-Topic: [PATCH] genirq: Increase the number of interrupters
Thread-Index: AQHYhrze4USA0Oy8jUywbP1lQPnHp61c1/2A
Date:   Thu, 23 Jun 2022 11:18:14 +0000
Message-ID: <7974b4d7782b4f8682547389d4f294f8@AcuMS.aculab.com>
References: <20220623031541.1716745-1-george.cherian@marvell.com>
In-Reply-To: <20220623031541.1716745-1-george.cherian@marvell.com>
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From: George Cherian
> Sent: 23 June 2022 04:16
> 
> Currently the maximum number of interrupters is capped at 8260 (64 +
> 8196) in most of the architectures were CONFIG_SPARSE_IRQ is selected.
> This upper limit is not sufficient for couple of existing SoC's from
> Marvell.
> For eg: Octeon TX2 series of processors support a maximum of 32K
> interrupters.
> 
> Bump up the upper limit from 8196 to 65536.

This seems to add 7kB of static data to the kernel just on
the off chance that some sparse interrupt numbers are large.

	David

> 
> Signed-off-by: George Cherian <george.cherian@marvell.com>
> ---
>  kernel/irq/internals.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h
> index f09c60393e559..9bb42757d4afc 100644
> --- a/kernel/irq/internals.h
> +++ b/kernel/irq/internals.h
> @@ -12,7 +12,7 @@
>  #include <linux/sched/clock.h>
> 
>  #ifdef CONFIG_SPARSE_IRQ
> -# define IRQ_BITMAP_BITS	(NR_IRQS + 8196)
> +# define IRQ_BITMAP_BITS	(NR_IRQS + 65536)
>  #else
>  # define IRQ_BITMAP_BITS	NR_IRQS
>  #endif
> --
> 2.25.1

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