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Message-ID: <3c088a9a511762f7868b10dbe431942d3724917a.camel@pengutronix.de>
Subject: Re: DMA-buf and uncached system memory
From:   Lucas Stach <l.stach@pengutronix.de>
To:     Christian =?ISO-8859-1?Q?K=F6nig?= <christian.koenig@amd.com>,
        Pekka Paalanen <ppaalanen@gmail.com>
Cc:     "Sharma, Shashank" <Shashank.Sharma@amd.com>,
        lkml <linux-kernel@vger.kernel.org>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        Nicolas Dufresne <nicolas@ndufresne.ca>,
        linaro-mm-sig@lists.linaro.org,
        Sumit Semwal <sumit.semwal@linaro.org>,
        linux-media <linux-media@vger.kernel.org>
Date:   Thu, 23 Jun 2022 14:14:48 +0200
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Am Donnerstag, dem 23.06.2022 um 13:54 +0200 schrieb Christian König:
> Am 23.06.22 um 13:29 schrieb Lucas Stach:
> > [SNIP]
> > > Well then the existing DMA-buf framework is not what you want to use for
> > > this.
> > > 
> > Sorry, but this is just ignoring reality. You try to flag 8+ years of
> > DMA-buf usage on non-coherent arches as "you shouldn't do this". At
> > this point there are probably a lot more users (drivers) of DMA-buf in
> > the kernel for devices, which are used on non-coherent arches, than
> > there are on coherent arches.
> 
> Well, it's my reality that people come up with bug reports about that 
> and we have been pushing back on this with the explanation "Hey this is 
> not supported" as long as I can think about it.
> 
> I mean I even had somebody from ARM which told me that this is not going 
> to work with our GPUs on a specific SoC. That there are ARM internal use 
> cases which just seem to work because all the devices are non-coherent 
> is completely new to me.
> 
Yes, trying to hook up a peripheral that assumes cache snooping in some
design details to a non coherent SoC may end up exploding in various
ways. On the other hand you can work around most of those assumptions
by marking the memory as uncached to the CPU, which may tank
performance, but will work from a correctness PoV.

> I'm as much surprised as you are about this lack of agreement about such 
> fundamental stuff.
> 
> > > > Non-coherent without explicit domain transfer points is just not going
> > > > to work. So why can't we solve the issue for DMA-buf in the same way as
> > > > the DMA API already solved it years ago: by adding the equivalent of
> > > > the dma_sync calls that do cache maintenance when necessary? On x86 (or
> > > > any system where things are mostly coherent) you could still no-op them
> > > > for the common case and only trigger cache cleaning if the importer
> > > > explicitly says that is going to do a non-snooping access.
> > > Because DMA-buf is a framework for buffer sharing between cache coherent
> > > devices which don't signal transitions.
> > > 
> > > We intentionally didn't implemented any of the dma_sync_* functions
> > > because that would break the intended use case.
> > > 
> > Non coherent access, including your non-snoop scanout, and no domain
> > transition signal just doesn't go together when you want to solve
> > things in a generic way.
> 
> Yeah, that's the stuff I totally agree on.
> 
> See we absolutely do have the requirement of implementing coherent 
> access without domain transitions for Vulkan and OpenGL+extensions.
> 
Coherent can mean 2 different things:
1. CPU cached with snooping from the IO device
2. CPU uncached

The Vulkan and GL "coherent" uses are really coherent without explicit
domain transitions, so on non coherent arches that require the
transitions the only way to implement this is by making the memory CPU
uncached. Which from a performance PoV will probably not be what app
developers expect, but will still expose the correct behavior.

> When we now have to introduce domain transitions to get non coherent 
> access working we are essentially splitting all the drivers into 
> coherent and non-coherent ones.
> 
> That doesn't sounds like it would improve interop.
> 
> > Remember that in a fully (not only IO) coherent system the CPU isn't
> > the only agent that may cache the content you are trying to access
> > here. The dirty cacheline could reasonably still be sitting in a GPU or
> > VPU cache, so you need some way to clean those cachelines, which isn't
> > a magic "importer knows how to call CPU cache clean instructions".
> 
> IIRC we do already have/had a SYNC_IOCTL for cases like this, but (I 
> need to double check as well, that's way to long ago) this was kicked 
> out because of the requirements above.
> 
The DMA_BUF_IOCTL_SYNC is available in upstream, with the explicit
documentation that "userspace can not rely on coherent access".

> > > You can of course use DMA-buf in an incoherent environment, but then you
> > > can't expect that this works all the time.
> > > 
> > > This is documented behavior and so far we have bluntly rejected any of
> > > the complains that it doesn't work on most ARM SoCs and I don't really
> > > see a way to do this differently.
> > Can you point me to that part of the documentation? A quick grep for
> > "coherent" didn't immediately turn something up within the DMA-buf
> > dirs.
> 
> Search for "cache coherency management". It's quite a while ago, but I 
> do remember helping to review that stuff.
> 
That only turns up the lines in DMA_BUF_IOCTL_SYNC doc, which are
saying the exact opposite of the DMA-buf is always coherent.

I also don't see why you think that both world views are so totally
different. We could just require explicit domain transitions for non-
snoop access, which would probably solve your scanout issue and would
not be a problem for most ARM systems, where we could no-op this if the
buffer is already in uncached memory and at the same time keep the "x86
assumes cached + snooped access by default" semantics.

Regards,
Lucas