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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y17-20020a056402359100b0043343b373e9si2681691edc.592.2022.06.24.02.22.33; Fri, 24 Jun 2022 02:22:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=N4Tmw0eP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231548AbiFXJUR (ORCPT + 99 others); Fri, 24 Jun 2022 05:20:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229936AbiFXJUP (ORCPT ); Fri, 24 Jun 2022 05:20:15 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFAC162C1F; Fri, 24 Jun 2022 02:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656062415; x=1687598415; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=uYD1uTF7xm0qgleE5UH18GfQqBuORkl6A9rKczOB9Ts=; b=N4Tmw0ePueqfPyj2GIrm/eg+nr5XGuf183QBPYLIr4PRM4c0vwaoccIO mU19fdIaroUiAYjKaf6n5EhL+yTk3qHKyw1f0tbAvgdSV6zSScawFABPt uGd9+wKthYAEcqKcnKEHF15h355uVR3nXjKoQlQCaqGf82geL6EK7oTy8 0=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 24 Jun 2022 02:20:14 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 24 Jun 2022 02:20:13 -0700 X-QCInternal: smtphost Received: from hu-krichai-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.110.37]) by ironmsg01-blr.qualcomm.com with ESMTP; 24 Jun 2022 14:49:54 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 9172C3D33; Fri, 24 Jun 2022 14:49:54 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, Krishna chaitanya chundru , Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas Subject: [PATCH v1 1/3] PCI: qcom: Add missing sc7280 clocks in PCIe driver Date: Fri, 24 Jun 2022 14:49:49 +0530 Message-Id: <1656062391-14567-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656062391-14567-1-git-send-email-quic_krichai@quicinc.com> References: <1656062391-14567-1-git-send-email-quic_krichai@quicinc.com> X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add missing clocks in the pcie driver. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2ea1375..a7202f0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1548,7 +1548,10 @@ static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, + .has_ddrss_sf_tbu_clk = true, .pipe_clk_need_muxing = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc8180x_cfg = { -- 2.7.4