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Date:   Fri, 24 Jun 2022 15:28:08 +0200
From:   Joerg Roedel <joro@8bytes.org>
To:     Robin Murphy <robin.murphy@arm.com>
Cc:     will@kernel.org, iommu@lists.linux-foundation.org,
        linux-kernel@vger.kernel.org, hch@lst.de, john.garry@huawei.com
Subject: Re: [PATCH v2] iommu/dma: Add config for PCI SAC address trick
Message-ID: <YrW76PPKadbZuN/3@8bytes.org>
References: <3f06994f9f370f9d35b2630ab75171ecd2065621.1654782107.git.robin.murphy@arm.com>
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 <653fba02-7eef-5f0d-66dd-7599af84db86@arm.com>
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On Thu, Jun 23, 2022 at 12:41:00PM +0100, Robin Murphy wrote:
> On 2022-06-23 12:33, Joerg Roedel wrote:
> > On Wed, Jun 22, 2022 at 02:12:39PM +0100, Robin Murphy wrote:
> > > Thanks for your bravery!
> > 
> > It already starts, with that patch I am getting:
> > 
> > 	xhci_hcd 0000:02:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x000f address=0xff00ffffffefe000 flags=0x0000]
> > 
> > In my kernel log. The device is an AMD XHCI controller and seems to
> > funciton normally after boot. The message disappears with
> > iommu.forcedac=0.
> > 
> > Need to look more into that...
> 
> Given how amd_iommu_domain_alloc() sets the domain aperture, presumably the
> DMA address allocated was 0xffffffffffefe000? Odd that it gets bits punched
> out in the middle rather than simply truncated off the top as I would have
> expected :/

So even more weird, as a workaround I changed the AMD IOMMU driver to
allocate a 4-level page-table and limit the DMA aperture to 48 bits. I
still get the same message.