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References: <20220624160117.3206-1-nikita.shubin@maquefel.me> <20220624160117.3206-4-nikita.shubin@maquefel.me>
In-Reply-To: <20220624160117.3206-4-nikita.shubin@maquefel.me>
From:   Atish Patra <atishp@atishpatra.org>
Date:   Fri, 24 Jun 2022 10:01:07 -0700
Message-ID: <CAOnJCU+B+dXXhqL6CYRG7Lhr_QWwyxrDZdGZG6HphnTEE9o5Mw@mail.gmail.com>
Subject: Re: [PATCH v4 3/5] perf arch events: riscv arch std event files
To:     Nikita Shubin <nikita.shubin@maquefel.me>
Cc:     Anup Patel <anup@brainfault.org>,
        =?UTF-8?B?Sm/Do28gTcOhcmlvIERvbWluZ29z?= 
        <joao.mario@tecnico.ulisboa.pt>, linux <linux@yadro.com>,
        Nikita Shubin <n.shubin@yadro.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@kernel.org>,
        Namhyung Kim <namhyung@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        linux-perf-users@vger.kernel.org,
        linux-riscv <linux-riscv@lists.infradead.org>
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On Fri, Jun 24, 2022 at 9:01 AM Nikita Shubin <nikita.shubin@maquefel.me> w=
rote:
>
> From: Nikita Shubin <n.shubin@yadro.com>
>
> cycles, time and instret counters are defined by RISC-V privileged
> spec and they should be available on any RISC-V implementation, epose the=
m
> to arch std event files, so they can be reused by particular PMU
> bindings.
>
> Derived-from-code-by: Jo=C3=A3o M=C3=A1rio Domingos <joao.mario@tecnico.u=
lisboa.pt>
> Signed-off-by: Nikita Shubin <n.shubin@yadro.com>

Why do we need this ? The PMU driver already parses the standard perf event=
s.
So you can pass -e cycles -e instructions.

Even though time is described as a counter and accessibility
controlled by mcounteren, you can not start/stop it (no bit in
mcountinhibit).
Thus, it can't be used from perf.

> ---
>  .../pmu-events/arch/riscv/riscv-generic.json  | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
>
> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/=
perf/pmu-events/arch/riscv/riscv-generic.json
> new file mode 100644
> index 000000000000..a7ffbe87a0f7
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
> @@ -0,0 +1,20 @@
> +[
> +  {
> +    "PublicDescription": "CPU Cycles",
> +    "EventCode": "0x00",
> +    "EventName": "riscv_cycles",
> +    "BriefDescription": "CPU cycles RISC-V generic counter"
> +  },
> +  {
> +    "PublicDescription": "CPU Time",
> +    "EventCode": "0x01",
> +    "EventName": "riscv_time",
> +    "BriefDescription": "CPU time RISC-V generic counter"
> +  },
> +  {
> +    "PublicDescription": "CPU Instructions",
> +    "EventCode": "0x02",
> +    "EventName": "riscv_instret",
> +    "BriefDescription": "CPU retired instructions RISC-V generic counter=
"
> +  }
> +]
> --
> 2.35.1
>


--=20
Regards,
Atish