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Message-ID: <e07e2591-6913-cb51-021b-125c3c60b2fc@kernel.org>
Date:   Fri, 24 Jun 2022 17:47:09 -0500
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Subject: Re: [PATCHv3] arm64: dts: altera: socfpga_stratix10: move clocks out
 of soc node
Content-Language: en-US
To:     niravkumar.l.rabara@intel.com
Cc:     devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org,
        linux-kernel@vger.kernel.org, robh+dt@kernel.org
References: <c90eb127-fa5a-2231-106d-5054e0097281@kernel.org>
 <20220624162159.3403541-1-niravkumar.l.rabara@intel.com>
From:   Dinh Nguyen <dinguyen@kernel.org>
In-Reply-To: <20220624162159.3403541-1-niravkumar.l.rabara@intel.com>
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On 6/24/22 11:21, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> The clocks are not part of the SoC but provided on the board
> (external oscillators). Moving them out of soc node.
> 
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>   .../boot/dts/altera/socfpga_stratix10.dtsi    | 56 +++++++++----------
>   .../dts/altera/socfpga_stratix10_socdk.dts    | 10 ++--
>   .../altera/socfpga_stratix10_socdk_nand.dts   | 10 ++--
>   3 files changed, 36 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index aa2bba75265f..5c7d926d18f7 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -97,6 +97,34 @@ intc: interrupt-controller@fffc1000 {
>   		      <0x0 0xfffc6000 0x0 0x2000>;
>   	};
>   
> +	clocks {
> +		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +		};
> +
> +		cb_intosc_ls_clk: cb-intosc-ls-clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +		};
> +
> +		f2s_free_clk: f2s-free-clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +		};
> +
> +		osc1: osc1 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +		};
> +
> +		qspi_clk: qspi-clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <200000000>;
> +		};
> +	};
> +
>   	soc {
>   		#address-cells = <1>;
>   		#size-cells = <1>;
> @@ -119,34 +147,6 @@ clkmgr: clock-controller@ffd10000 {
>   			#clock-cells = <1>;
>   		};
>   
> -		clocks {
> -			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
> -				#clock-cells = <0>;
> -				compatible = "fixed-clock";
> -			};
> -
> -			cb_intosc_ls_clk: cb-intosc-ls-clk {
> -				#clock-cells = <0>;
> -				compatible = "fixed-clock";
> -			};
> -
> -			f2s_free_clk: f2s-free-clk {
> -				#clock-cells = <0>;
> -				compatible = "fixed-clock";
> -			};
> -
> -			osc1: osc1 {
> -				#clock-cells = <0>;
> -				compatible = "fixed-clock";
> -			};
> -
> -			qspi_clk: qspi-clk {
> -				#clock-cells = <0>;
> -				compatible = "fixed-clock";
> -				clock-frequency = <200000000>;
> -			};
> -		};
> -
>   		gmac0: ethernet@ff800000 {
>   			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
>   			reg = <0xff800000 0x2000>;
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
> index 5159cd5771dc..48424e459f12 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
> @@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
>   	};
>   
>   	soc {
> -		clocks {
> -			osc1 {
> -				clock-frequency = <25000000>;
> -			};
> -		};
> -
>   		eccmgr {
>   			sdmmca-ecc@ff8c8c00 {
>   				compatible = "altr,socfpga-s10-sdmmc-ecc",
> @@ -113,6 +107,10 @@ &mmc {
>   	bus-width = <4>;
>   };
>   
> +&osc1 {
> +	clock-frequency = <25000000>;
> +};
> +
>   &uart0 {
>   	status = "okay";
>   };
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
> index 0ab676c639a1..847a7c01f5af 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
> @@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
>   	};
>   
>   	soc {
> -		clocks {
> -			osc1 {
> -				clock-frequency = <25000000>;
> -			};
> -		};
> -
>   		eccmgr {
>   			sdmmca-ecc@ff8c8c00 {
>   				compatible = "altr,socfpga-s10-sdmmc-ecc",
> @@ -126,6 +120,10 @@ partition@200000 {
>   	};
>   };
>   
> +&osc1 {
> +	clock-frequency = <25000000>;
> +};
> +
>   &uart0 {
>   	status = "okay";
>   };


Applied!

Thanks,
Dinh