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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Sat, 25 Jun 2022 13:48:08 +0100
Message-ID: <CA+V-a8td93QOCC8cHLEPaba-hnX2gjydmKTbaCrF+zgH7hH8Jg@mail.gmail.com>
Subject: Re: [PATCH v5 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller driver
To:     Marc Zyngier <maz@kernel.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Andy Shevchenko <andy.shevchenko@gmail.com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        linux-tegra <linux-tegra@vger.kernel.org>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Phil Edworthy <phil.edworthy@renesas.com>,
        Biju Das <biju.das.jz@bp.renesas.com>
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Hi Marc,

On Sat, Jun 25, 2022 at 1:08 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sat, 25 Jun 2022 11:54:44 +0100,
> "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Marc,
> >
> > Thank you for the review.
> >
> > On Sat, Jun 25, 2022 at 10:30 AM Marc Zyngier <maz@kernel.org> wrote:
> > >
> > > On Mon, 23 May 2022 18:42:35 +0100,
> > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > >
>
> [...]
>
> > > > +static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned in=
t virq,
> > > > +                         unsigned int nr_irqs, void *arg)
> > > > +{
> > > > +     struct rzg2l_irqc_priv *priv =3D domain->host_data;
> > > > +     unsigned long *chip_data =3D NULL;
> > >
> > > Why the init to NULL?
> > >
> > Can be dropped.
> >
> > > > +     struct irq_fwspec spec;
> > > > +     irq_hw_number_t hwirq;
> > > > +     int tint =3D -EINVAL;
> > > > +     unsigned int type;
> > > > +     unsigned int i;
> > > > +     int ret;
> > > > +
> > > > +     ret =3D irq_domain_translate_twocell(domain, arg, &hwirq, &ty=
pe);
> > > > +     if (ret)
> > > > +             return ret;
> > > > +
> > > > +     /*
> > > > +      * For TINT interrupts ie where pinctrl driver is child of ir=
qc domain
> > > > +      * the hwirq and TINT are encoded in fwspec->param[0].
> > > > +      * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bit=
s and TINT
> > > > +      * from 16-31 bits. TINT from the pinctrl driver needs to be =
programmed
> > > > +      * in IRQC registers to enable a given gpio pin as interrupt.
> > > > +      */
> > > > +     if (hwirq > IRQC_IRQ_COUNT) {
> > > > +             tint =3D TINT_EXTRACT_GPIOINT(hwirq);
> > > > +             hwirq =3D TINT_EXTRACT_HWIRQ(hwirq);
> > > > +
> > > > +             if (hwirq < IRQC_TINT_START)
> > > > +                     return -EINVAL;
> > > > +     }
> > > > +
> > > > +     if (hwirq > (IRQC_NUM_IRQ - 1))
> > > > +             return -EINVAL;
> > > > +
> > > > +     chip_data =3D kzalloc(sizeof(*chip_data), GFP_KERNEL);
> > >
> > > Are we really allocating an unsigned long for something that already
> > > fits in something that is pointer-sized?
> > >
> > I think I received some feedback to use unsigned long.  Let me know
> > what you want me to use here.
>
> I think this is just a waste of memory, but I don't really care.
>
Is there any better way I can handle it?

> >
> > > > +     if (!chip_data)
> > > > +             return -ENOMEM;
> > > > +     *chip_data =3D tint;
> > >
> > > So here, *chip_data can be set to -EINVAL if hwirq <=3D IRQC_IRQ_COUN=
T?
> > > This can't be right.
> > >
> > Yes *chip_data can be -EINVAL. IRQC block handles IRQ0-7 and
> > GPIOINT0-122. So the -EINVAL here is for IRQ0-7 case were dont
> > required the chip data in the call backs hence -EINVAL, Whereas for
> > GPIOINT0-122 we need chip_data in the callbacks as this value needs to
> > be programmed in the hardware registers.
>
> I can't see anything that checks it (let alone the difference in
> types). And if it isn't checked, this means that the allocation is
> pointless.
>
There are checks for example below:

static void rzg2l_irqc_irq_enable(struct irq_data *d)
{
    unsigned int hw_irq =3D irqd_to_hwirq(d);

    if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
        struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
        unsigned long chip_data =3D *(unsigned long *)d->chip_data;
        u32 offset =3D hw_irq - IRQC_TINT_START;
        u32 tssr_offset =3D TSSR_OFFSET(offset);
        u8 tssr_index =3D TSSR_INDEX(offset);
        u32 reg;

        raw_spin_lock(&priv->lock);
        reg =3D readl_relaxed(priv->base + TSSR(tssr_index));
        reg |=3D (TIEN | chip_data) << TSSEL_SHIFT(tssr_offset);
        writel_relaxed(reg, priv->base + TSSR(tssr_index));
        raw_spin_unlock(&priv->lock);
    }
    irq_chip_enable_parent(d);
}

This check hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ here
would mean its GPIOINT0-122 and then the chip data will be used.

> >
> > > > +
> > > > +     ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &i=
rqc_chip,
> > > > +                                         chip_data);
> > > > +     if (ret) {
> > > > +             kfree(chip_data);
> > > > +             return ret;
> > > > +     }
> > > > +
> > > > +     spec.fwnode =3D domain->parent->fwnode;
> > > > +     spec.param_count =3D priv->map[hwirq].args_count;
> > > > +     for (i =3D 0; i < spec.param_count; i++)
> > > > +             spec.param[i] =3D priv->map[hwirq].args[i];
> > >
> > > Why isn't that simply:
> > >
> > >         spec =3D priv->map[hwirq];
> > >
> > spec is of type =E2=80=98struct irq_fwspec=E2=80=99 and map is of type =
=E2=80=98struct of_phandle_args=E2=80=99.
> >
> > > as this really is the interrupt you want to map to?
> > >
> > Yes.
> >
> > > > +
> > > > +     ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &=
spec);
> > >
> > > or even better:
> > >
> > >         ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
> > >                                            &priv->map[hwirq]);
> > >
> > Does not work as map is of type =E2=80=98struct of_phandle_args=E2=80=
=99.
>
> Which begs the question: why don't you convert it to an irq_fwspec the
> first place and be done with it?
>
Right..
> >
> > > > +     if (ret)
> > > > +             kfree(chip_data);
> > > > +
> > > > +     return ret;
> > > > +}
> > > > +
> > > > +static void rzg2l_irqc_domain_free(struct irq_domain *domain, unsi=
gned int virq,
> > > > +                                unsigned int nr_irqs)
> > > > +{
> > > > +     struct irq_data *d;
> > > > +
> > > > +     d =3D irq_domain_get_irq_data(domain, virq);
> > > > +     if (d)
> > > > +             kfree(d->chip_data);
> > > > +
> > > > +     irq_domain_free_irqs_common(domain, virq, nr_irqs);
> > > > +}
> > > > +
> > > > +static const struct irq_domain_ops rzg2l_irqc_domain_ops =3D {
> > > > +     .alloc =3D rzg2l_irqc_alloc,
> > > > +     .free =3D rzg2l_irqc_domain_free,
> > > > +     .translate =3D irq_domain_translate_twocell,
> > > > +};
> > > > +
> > > > +static int rzg2l_irqc_parse_map(struct rzg2l_irqc_priv *priv,
> > > > +                             struct device_node *np)
>
> nit: this function could afford being renamed to something more
> correct. It really doesn't map anything, only retrieves the output
> interrupts.
>
Sure will do.

> > > > +{
> > > > +     unsigned int i;
> > > > +     int ret;
> > > > +
> > > > +     for (i =3D 0; i < IRQC_NUM_IRQ; i++) {
> > > > +             ret =3D of_irq_parse_one(np, i, &priv->map[i]);
>
> Make map an array of irq_fwspec, and use of_phandle_args_to_fwspec()
> for the conversion.
>
... Good point, will do.

> > > > +             if (ret)
> > > > +                     return ret;
> > > > +     }
> > > > +
> > > > +     return 0;
> > > > +}
> > > > +
> > > > +static int rzg2l_irqc_init(struct device_node *node, struct device=
_node *parent)
> > > > +{
> > > > +     struct irq_domain *irq_domain, *parent_domain;
> > > > +     struct platform_device *pdev;
> > > > +     struct reset_control *resetn;
> > > > +     struct rzg2l_irqc_priv *priv;
> > > > +     int ret;
> > > > +
> > > > +     pdev =3D of_find_device_by_node(node);
> > > > +     if (!pdev)
> > > > +             return -ENODEV;
> > > > +
> > > > +     parent_domain =3D irq_find_host(parent);
> > > > +     if (!parent_domain) {
> > > > +             dev_err(&pdev->dev, "cannot find parent domain\n");
> > > > +             return -ENODEV;
> > > > +     }
> > > > +
> > > > +     priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > > > +     if (!priv)
> > > > +             return -ENOMEM;
> > > > +
> > > > +     priv->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0=
, NULL);
> > > > +     if (IS_ERR(priv->base))
> > > > +             return PTR_ERR(priv->base);
> > > > +
> > > > +     ret =3D rzg2l_irqc_parse_map(priv, node);
> > > > +     if (ret) {
> > > > +             dev_err(&pdev->dev, "cannot parse interrupts: %d\n", =
ret);
> > > > +             return ret;
> > > > +     }
> > > > +
> > > > +     resetn =3D devm_reset_control_get_exclusive_by_index(&pdev->d=
ev, 0);
> > > > +     if (IS_ERR(resetn))
> > > > +             return IS_ERR(resetn);
> > > > +
> > > > +     ret =3D reset_control_deassert(resetn);
> > > > +     if (ret) {
> > > > +             dev_err(&pdev->dev, "failed to deassert resetn pin, %=
d\n", ret);
> > > > +             return ret;
> > > > +     }
> > > > +
> > > > +     pm_runtime_enable(&pdev->dev);
> > > > +     ret =3D pm_runtime_resume_and_get(&pdev->dev);
> > > > +     if (ret < 0) {
> > > > +             dev_err(&pdev->dev, "pm_runtime_resume_and_get failed=
: %d\n", ret);
> > > > +             goto pm_disable;
> > > > +     }
> > >
> > > If using runtime PM, why isn't the core IRQ code made aware of this
> > > dependency by registering the device with irq_domain_set_pm_device()
> > > instead of leaving it enabled forever?
> > >
> > Ouch will add irq_domain_set_pm_device() below.
>
> You'll need a bit more than that. You'll either need to take a PM
> reference on each alloc, or improve irq_chip_pm_{get,put}() to talk
> the hierarchy.
>
Aha I see.

> That's probably a separate patch.
>
Agreed will make it a separate patch, once the driver gets in.


Cheers,
Prabhakar