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Date:   Sat, 25 Jun 2022 17:09:46 +0100
Message-ID: <87y1xkencl.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Andy Shevchenko <andy.shevchenko@gmail.com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        linux-tegra <linux-tegra@vger.kernel.org>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>,
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        Phil Edworthy <phil.edworthy@renesas.com>,
        Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v5 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller driver
In-Reply-To: <CA+V-a8td93QOCC8cHLEPaba-hnX2gjydmKTbaCrF+zgH7hH8Jg@mail.gmail.com>
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        <871qvdf5tb.wl-maz@kernel.org>
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        <87fsjt2bep.wl-maz@kernel.org>
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On Sat, 25 Jun 2022 13:48:08 +0100,
"Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> 
> Hi Marc,
> 
> On Sat, Jun 25, 2022 at 1:08 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Sat, 25 Jun 2022 11:54:44 +0100,
> > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > >
> > > Hi Marc,
> > >
> > > Thank you for the review.
> > >
> > > On Sat, Jun 25, 2022 at 10:30 AM Marc Zyngier <maz@kernel.org> wrote:
> > > >
> > > > On Mon, 23 May 2022 18:42:35 +0100,
> > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > >
> >
> > [...]
> >
> > > > > +static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
> > > > > +                         unsigned int nr_irqs, void *arg)
> > > > > +{
> > > > > +     struct rzg2l_irqc_priv *priv = domain->host_data;
> > > > > +     unsigned long *chip_data = NULL;
> > > >
> > > > Why the init to NULL?
> > > >
> > > Can be dropped.
> > >
> > > > > +     struct irq_fwspec spec;
> > > > > +     irq_hw_number_t hwirq;
> > > > > +     int tint = -EINVAL;
> > > > > +     unsigned int type;
> > > > > +     unsigned int i;
> > > > > +     int ret;
> > > > > +
> > > > > +     ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
> > > > > +     if (ret)
> > > > > +             return ret;
> > > > > +
> > > > > +     /*
> > > > > +      * For TINT interrupts ie where pinctrl driver is child of irqc domain
> > > > > +      * the hwirq and TINT are encoded in fwspec->param[0].
> > > > > +      * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
> > > > > +      * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
> > > > > +      * in IRQC registers to enable a given gpio pin as interrupt.
> > > > > +      */
> > > > > +     if (hwirq > IRQC_IRQ_COUNT) {
> > > > > +             tint = TINT_EXTRACT_GPIOINT(hwirq);
> > > > > +             hwirq = TINT_EXTRACT_HWIRQ(hwirq);
> > > > > +
> > > > > +             if (hwirq < IRQC_TINT_START)
> > > > > +                     return -EINVAL;
> > > > > +     }
> > > > > +
> > > > > +     if (hwirq > (IRQC_NUM_IRQ - 1))
> > > > > +             return -EINVAL;
> > > > > +
> > > > > +     chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
> > > >
> > > > Are we really allocating an unsigned long for something that already
> > > > fits in something that is pointer-sized?
> > > >
> > > I think I received some feedback to use unsigned long.  Let me know
> > > what you want me to use here.
> >
> > I think this is just a waste of memory, but I don't really care.
> >
> Is there any better way I can handle it?

How about (shock, horror) a cast?

> 
> > >
> > > > > +     if (!chip_data)
> > > > > +             return -ENOMEM;
> > > > > +     *chip_data = tint;
> > > >
> > > > So here, *chip_data can be set to -EINVAL if hwirq <= IRQC_IRQ_COUNT?
> > > > This can't be right.
> > > >
> > > Yes *chip_data can be -EINVAL. IRQC block handles IRQ0-7 and
> > > GPIOINT0-122. So the -EINVAL here is for IRQ0-7 case were dont
> > > required the chip data in the call backs hence -EINVAL, Whereas for
> > > GPIOINT0-122 we need chip_data in the callbacks as this value needs to
> > > be programmed in the hardware registers.
> >
> > I can't see anything that checks it (let alone the difference in
> > types). And if it isn't checked, this means that the allocation is
> > pointless.
> >
> There are checks for example below:
> 
> static void rzg2l_irqc_irq_enable(struct irq_data *d)
> {
>     unsigned int hw_irq = irqd_to_hwirq(d);
> 
>     if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
>         struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
>         unsigned long chip_data = *(unsigned long *)d->chip_data;
>         u32 offset = hw_irq - IRQC_TINT_START;
>         u32 tssr_offset = TSSR_OFFSET(offset);
>         u8 tssr_index = TSSR_INDEX(offset);
>         u32 reg;
> 
>         raw_spin_lock(&priv->lock);
>         reg = readl_relaxed(priv->base + TSSR(tssr_index));
>         reg |= (TIEN | chip_data) << TSSEL_SHIFT(tssr_offset);
>         writel_relaxed(reg, priv->base + TSSR(tssr_index));
>         raw_spin_unlock(&priv->lock);
>     }
>     irq_chip_enable_parent(d);
> }
> 
> This check hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ here
> would mean its GPIOINT0-122 and then the chip data will be used.

That doesn't check the content of chip_data if outside of this
condition. Nonetheless, you allocate an unsigned long to store
-EINVAL. Not only this is a pointless allocation, but you use it to
store something that you never retrieve the first place. Don't you see
the problem?

	M.

-- 
Without deviation from the norm, progress is not possible.