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From:   Samuel Holland <samuel@sholland.org>
To:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Prabhakar <prabhakar.csengg@gmail.com>,
        Marc Zyngier <maz@kernel.org>,
        Sagar Kadam <sagar.kadam@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>
Cc:     linux-renesas-soc@vger.kernel.org, Guo Ren <guoren@kernel.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Thomas Gleixner <tglx@linutronix.de>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Samuel Holland <samuel@sholland.org>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH v1 2/3] irqchip/sifive-plic: Name the chip more generically
Date:   Mon, 27 Jun 2022 00:12:56 -0500
Message-Id: <20220627051257.38543-3-samuel@sholland.org>
In-Reply-To: <20220627051257.38543-1-samuel@sholland.org>
References: <20220627051257.38543-1-samuel@sholland.org>
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The interface for SiFive's PLIC was adopted and clarified by RISC-V as
the standard PLIC interface. Now that several PLIC implementations by
different vendors share this same interface, it is somewhat misleading
to report "SiFive PLIC" to userspace, when no SiFive hardware may be
present. This is especially the case when some implementations are
subtly incompatible with the binding and behavior of the SiFive PLIC,
yet are similar enough to share a driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/irqchip/irq-sifive-plic.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index bb87e4c3b88e..90515865af08 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -28,6 +28,11 @@
  * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
  * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
  * Spec.
+ *
+ * The PLIC behavior and memory map is futher formalized as an official RISC-V
+ * specification:
+ *
+ *     https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc
  */
 
 #define MAX_DEVICES			1024
@@ -177,12 +182,12 @@ static void plic_irq_eoi(struct irq_data *d)
 }
 
 static struct irq_chip plic_chip = {
-	.name		= "SiFive PLIC",
-	.irq_mask	= plic_irq_mask,
-	.irq_unmask	= plic_irq_unmask,
-	.irq_eoi	= plic_irq_eoi,
+	.name			= "PLIC",
+	.irq_mask		= plic_irq_mask,
+	.irq_unmask		= plic_irq_unmask,
+	.irq_eoi		= plic_irq_eoi,
 #ifdef CONFIG_SMP
-	.irq_set_affinity = plic_set_affinity,
+	.irq_set_affinity	= plic_set_affinity,
 #endif
 };
 
-- 
2.35.1