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Mon, 27 Jun 2022 06:40:44 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Sun, 26 Jun 2022 23:40:32 -0700 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Sun, 26 Jun 2022 23:40:32 -0700 Envelope-to: monstr@monstr.eu, arnd@arndb.de, shorne@gmail.com, ebiederm@xmission.com, appanad@amd.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sam@ravnborg.org Received: from [10.140.6.6] (port=50182 helo=xhdappanad40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o5iQB-000Bsc-UW; Sun, 26 Jun 2022 23:40:32 -0700 From: Appana Durga Kedareswara rao To: , , , , CC: , , , Appana Durga Kedareswara rao Subject: [PATCH 1/3] microblaze: Add xmb_manager_register function Date: Mon, 27 Jun 2022 12:10:22 +0530 Message-ID: <20220627064024.771037-2-appana.durga.rao@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627064024.771037-1-appana.durga.rao@xilinx.com> References: <20220627064024.771037-1-appana.durga.rao@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aaa7e760-a696-4c86-6a43-08da5807f660 X-MS-TrafficTypeDiagnostic: DM5PR02MB2810:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2022 06:40:44.7094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aaa7e760-a696-4c86-6a43-08da5807f660 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0035.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2810 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Triple Modular Redundancy (TMR) Microblaze solution provides soft error injection, detection, correction and recovery for Microblaze cores in the system. The Xilinx/AMD Triple Modular Redundancy (TMR) solution in Vivado provides all the necessary building blocks to implement a redundant triplicated MicroBlaze subsystem. This processing subsystem is fault-tolerant and continues to operate nominally after encountering an error. Together with the capability to detect and recover from errors, the implementation ensures the reliability of the entire subsystem. When the break vector gets asserted because of error injection, the break signal must be blocked before exiting from the break handler, This commit adds support for xmb_manager_register api which updates the TMR manager address and control register and error count and reset callback function arguments, which will be used by the break handler to block the break and call the error count callback function and reset callback function. Signed-off-by: Appana Durga Kedareswara rao --- arch/microblaze/Kconfig | 10 +++++ .../include/asm/xilinx_mb_manager.h | 21 +++++++++ arch/microblaze/kernel/entry.S | 44 +++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 arch/microblaze/include/asm/xilinx_mb_manager.h diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 8cf429ad1c84..7bcab7357f42 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -206,6 +206,16 @@ config TASK_SIZE hex "Size of user task space" if TASK_SIZE_BOOL default "0x80000000" +config MB_MANAGER + bool "Support for Microblaze Manager" + depends on ADVANCED_OPTIONS + help + This option enables API for configuring the MicroBlaze manager + control register, which is consumed by the break handler to + block the break. + + Say N here unless you know what you are doing. + endmenu menu "Bus Options" diff --git a/arch/microblaze/include/asm/xilinx_mb_manager.h b/arch/microblaze/include/asm/xilinx_mb_manager.h new file mode 100644 index 000000000000..392c3aa278dc --- /dev/null +++ b/arch/microblaze/include/asm/xilinx_mb_manager.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Xilinx, Inc. + */ +#ifndef _XILINX_MB_MANAGER_H +#define _XILINX_MB_MANAGER_H + +#include + +/* + * When the break vector gets asserted because of error injection, the break + * signal must be blocked before exiting from the break handler, Below api + * updates the manager address and control register and error counter callback + * arguments, which will be used by the break handler to block the break and + * call the callback function. + */ +void xmb_manager_register(uintptr_t phys_baseaddr, u32 cr_val, + void (*callback)(void *data), + void *priv, void (*reset_callback)(void *data)); + +#endif /* _XILINX_MB_MANAGER_H */ diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S index b179f8f6d287..b8e1dfe02d58 100644 --- a/arch/microblaze/kernel/entry.S +++ b/arch/microblaze/kernel/entry.S @@ -957,6 +957,50 @@ ENTRY(_switch_to) rtsd r15, 8 nop +#ifdef CONFIG_MB_MANAGER +.section .data +.global xmb_manager_dev +.global xmb_manager_baseaddr +.global xmb_manager_crval +.global xmb_manager_callback +.global xmb_manager_reset_callback +.align 4 +xmb_manager_dev: + .long 0 +xmb_manager_baseaddr: + .long 0 +xmb_manager_crval: + .long 0 +xmb_manager_callback: + .long 0 +xmb_manager_reset_callback: + .long 0 + +/* + * When the break vector gets asserted because of error injection, + * the break signal must be blocked before exiting from the + * break handler, Below api updates the manager address and + * control register and error count callback arguments, + * which will be used by the break handler to block the + * break and call the callback function. + */ +.global xmb_manager_register +.section .text +.align 2 +.ent xmb_manager_register +.type xmb_manager_register, @function +xmb_manager_register: + swi r5, r0, xmb_manager_baseaddr + swi r6, r0, xmb_manager_crval + swi r7, r0, xmb_manager_callback + swi r8, r0, xmb_manager_dev + swi r9, r0, xmb_manager_reset_callback + + rtsd r15, 8; + nop; +.end xmb_manager_register +#endif + ENTRY(_reset) VM_OFF brai 0; /* Jump to reset vector */ -- 2.25.1