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Date:   Mon, 27 Jun 2022 09:38:15 +0200
From:   =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <clement.leger@bootlin.com>
To:     Vladimir Oltean <olteanv@gmail.com>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Vivien Didelot <vivien.didelot@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        "David S . Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Giuseppe Cavallaro <peppe.cavallaro@st.com>,
        Jose Abreu <joabreu@synopsys.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Herve Codina <herve.codina@bootlin.com>,
        =?UTF-8?B?TWlxdcOobA==?= Raynal <miquel.raynal@bootlin.com>,
        Milan Stevanovic <milan.stevanovic@se.com>,
        Jimmy Lalande <jimmy.lalande@se.com>,
        Pascal Eberhard <pascal.eberhard@se.com>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org
Subject: Re: [PATCH net-next v9 00/16] add support for Renesas RZ/N1
 ethernet subsystem devices
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        <20220624214330.aezwdsirjvvoha45@skbuf>
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Le Sat, 25 Jun 2022 00:43:30 +0300,
Vladimir Oltean <olteanv@gmail.com> a =C3=A9crit :

> On Fri, Jun 24, 2022 at 04:39:45PM +0200, Cl=C3=A9ment L=C3=A9ger wrote:
> > The Renesas RZ/N1 SoCs features an ethernet subsystem which contains
> > (most notably) a switch, two GMACs, and a MII converter [1]. This
> > series adds support for the switch and the MII converter.
> >=20
> > The MII converter present on this SoC has been represented as a PCS
> > which sit between the MACs and the PHY. This PCS driver is probed from
> > the device-tree since it requires to be configured. Indeed the MII
> > converter also contains the registers that are handling the muxing of
> > ports (Switch, MAC, HSR, RTOS, etc) internally to the SoC.
> >=20
> > The switch driver is based on DSA and exposes 4 ports + 1 CPU
> > management port. It include basic bridging support as well as FDB and
> > statistics support.
> >=20
> > Link: [1] https://www.renesas.com/us/en/document/mah/rzn1d-group-rzn1s-=
group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals
> >=20
> > -----
> > Changes in V9:
> > - Cover letter:
> >   - Remove comment about RZN1 patches that are now in the master branch.
> > - Commits:
> >   - Add Vladimir Oltean Reviewed-by
> > - PCS:
> >   - Add "Depends on OF" for PCS_RZN1_MIIC due to error found by intel
> >     kernel test robot <lkp@intel.com>.
> >   - Check return value of of_property_read_u32() for
> >     "renesas,miic-switch-portin" property before setting conf.
> >   - Return miic_parse_dt() return value in miic_probe() on error
> > - Switch:
> >   - Add "Depends on OF" for NET_DSA_RZN1_A5PSW due to errors found by
> >     intel kernel test robot <lkp@intel.com>.
> > - DT:
> >   - Add spaces between switch port and '{' =20
>=20
> I took one more look through the series and this looks good, thanks.

Hi Vladimir,

Thanks for the review.

Cl=C3=A9ment

>=20
> Reviewed-by: Vladimir Oltean <olteanv@gmail.com>


--=20
Cl=C3=A9ment L=C3=A9ger,
Embedded Linux and Kernel engineer at Bootlin
https://bootlin.com