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Date:   Mon, 27 Jun 2022 11:24:13 +0200
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Subject: Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
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To:     Conor.Dooley@microchip.com, damien.lemoal@opensource.wdc.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org
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From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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On 27/06/2022 09:06, Conor.Dooley@microchip.com wrote:
> 
> 
> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>
>>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>
>>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>>
>>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>>> ---
>>>>>>> ---
>>>>>>>    arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>>>    1 file changed, 6 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>>
>>>>>>>         sram: memory@80000000 {
>>>>>>>                 device_type = "memory";
>>>>>>> -             compatible = "canaan,k210-sram";
>>>>>>>                 reg = <0x80000000 0x400000>,
>>>>>>>                       <0x80400000 0x200000>,
>>>>>>>                       <0x80600000 0x200000>;
>>>>>>> -             reg-names = "sram0", "sram1", "aisram";
>>>>>>> -             clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>>> -                      <&sysclk K210_CLK_SRAM1>,
>>>>>>> -                      <&sysclk K210_CLK_AI>;
>>>>>>> -             clock-names = "sram0", "sram1", "aisram";
>>>>>>>         };
>>>>>>
>>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>>
>>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>>> the dtbs_check complaints.
>>>>>
>>>>> I guess the alternative approach of actually documenting the compatible
>>>>> would be more palatable?
>>>>
>>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>>> warnings.
>>>
>>> Hmm looks like that approach contradicts the dt-schema;
>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>>
>>> @Rob,Krzysztof what is one meant to do here?
>>
>> Why do you think it contradict bindings? Bindings for memory allow
> 
> Because when I tried to write the binding, the memory node complained
> about the clock properties etc and referenced the dt-schema (which
> for memory@foo nodes has additionalProperties: false.

Ah, I see, I looked at wrong level. Indeed memory node cannot have
anything else.

> 
>> additional properties, so you just need to create binding for this one.
>> And make it a correct binding, IOW, be sure that these clocks are real etc.
>>
>> Although usually we had separate bindings (and device drivers) for
>> memory controllers, instead of including them in the "memory" node.
> 
> I guess changing to that format would probably require some changes on
> the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
> looks like the clocks etc go in a controller node, which seems like a
> "better" way of doing it - 

Yes, because I think memory node is kind of special. It describes the
physical memory layout for the system, not the memory controller or
memory characteristics (like timings).

What U-Boot needs is indeed memory controller node. It's not only
calxeda but also few others using JEDEC LPDDR bindings.

> but would break existing dts in U-Boot
> without changes to handle both methods there.

Yes, that's a bit inconvenient but also a price someone has to pay for
introducing DTS properties without bindings.

Best regards,
Krzysztof