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Date:   Mon, 27 Jun 2022 16:01:31 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     Yicong Yang <yangyicong@huawei.com>
Cc:     Greg KH <gregkh@linuxfoundation.org>, yangyicong@hisilicon.com,
        helgaas@kernel.org, lorenzo.pieralisi@arm.com,
        mathieu.poirier@linaro.org, suzuki.poulose@arm.com,
        jonathan.cameron@huawei.com, robin.murphy@arm.com,
        leo.yan@linaro.org, mark.rutland@arm.com, will@kernel.org,
        joro@8bytes.org, shameerali.kolothum.thodi@huawei.com,
        mingo@redhat.com, linux-kernel@vger.kernel.org,
        john.garry@huawei.com, linux-arm-kernel@lists.infradead.org,
        linux-pci@vger.kernel.org, linux-perf-users@vger.kernel.org,
        iommu@lists.linux-foundation.org, prime.zeng@huawei.com,
        liuqi115@huawei.com, james.clark@arm.com,
        zhangshaokun@hisilicon.com, linuxarm@huawei.com,
        alexander.shishkin@linux.intel.com, acme@kernel.org
Subject: Re: [PATCH v9 0/8] Add support for HiSilicon PCIe Tune and Trace
 device
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References: <20220606115555.41103-1-yangyicong@hisilicon.com>
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On Mon, Jun 27, 2022 at 09:25:42PM +0800, Yicong Yang wrote:
> On 2022/6/27 21:12, Greg KH wrote:
> > On Mon, Jun 27, 2022 at 07:18:12PM +0800, Yicong Yang wrote:
> >> Hi Greg,
> >>
> >> Since the kernel side of this device has been reviewed for 8 versions with
> >> all comments addressed and no more comment since v9 posted in 5.19-rc1,
> >> is it ok to merge it first (for Patch 1-3 and 7-8)?
> > 
> > I am not the maintainer of this subsystem, so I do not understand why
> > you are asking me :(
> > 
> 
> I checked the log of drivers/hwtracing and seems patches of coresight/intel_th/stm
> applied by different maintainers and I see you applied some patches of intel_th/stm.
> Should any of these three maintainers or you can help applied this?

I was hoping Mark would have a look, since he knows this ARM stuff
better than me. But ISTR he's somewhat busy atm too. But an ACK from the
CoreSight people would also be appreciated.

And Arnaldo usually doesn't pick up the userspace perf bits until the
kernel side is sorted.