Date: Sat, 26 May 2007 17:55:15 -0600
From: Grant Grundler <grundler@parisc-linux.org>
To: David Miller <davem@davemloft.net>
Cc: abraham.manu@gmail.com, rdreier@cisco.com, greg@kroah.com,
       linux-pci@atrey.karlin.mff.cuni.cz, linux-kernel@vger.kernel.org
Subject: Re: PCIE
Message-ID: <20070526235515.GA31023@colo.lackof.org>
References: <46561287.8020103@gmail.com> <ada1wh560u1.fsf@cisco.com> <46584C30.4030206@gmail.com> <20070526.154910.78725926.davem@davemloft.net>
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On Sat, May 26, 2007 at 03:49:10PM -0700, David Miller wrote:
> From: Manu Abraham <abraham.manu@gmail.com>
> Date: Sat, 26 May 2007 19:03:12 +0400
> 
> > i presume then i shouldn't be using IRQF_SHARED, if using MSI.
> 
> That's actually a really good question.
> 
> It is likely architecture dependant whether the PCI controller wires
> unique MSI interrupts to shared cpu interrupt lines.

MSI (and MSI-X) vectors are required to be exclusive.
I submitted that change to pci.txt last year:
	http://lkml.org/lkml/2006/12/25/2

and ISTR I've posted that bit of the PCI spec a few years ago.
But it probably was to linux-pci mailing list only.

> I can imagine many systems where the cpu simply doesn't have enough
> interrupt pins to uniquely identify every possible MSI interrupt
> source.

The cpus haven't been using interrupt pins for a long time now.
Anything with a Local-xAPIC is already using transactions to
signal interrupts even if the OS isn't aware of it.

hth,
grant

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