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Date: Sun, 27 May 2007 05:01:02 +0400
From: Manu Abraham <abraham.manu@gmail.com>
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To: David Miller <davem@davemloft.net>
CC: grundler@parisc-linux.org, rdreier@cisco.com, greg@kroah.com,
       linux-pci@atrey.karlin.mff.cuni.cz, linux-kernel@vger.kernel.org
Subject: Re: PCIE
References: <20070526235515.GA31023@colo.lackof.org>	<20070526.170039.119261389.davem@davemloft.net>	<20070527001631.GC31023@colo.lackof.org> <20070526.173037.45196275.davem@davemloft.net>
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David Miller wrote:
> From: Grant Grundler <grundler@parisc-linux.org>
> Date: Sat, 26 May 2007 18:16:31 -0600
> 
>> Are they really? The device is generating the transaction on the bus.
>> The PCI host controller (in general) will be routing that transaction
>> to wherever the "dest addr" of the MSI lives. It doesn't have to be
>> in the CPU but it will certainly be a proxy for that CPU if it's not.
>> We won't care if the proxy only have one IRQ line going to the CPU
>> as long as the de-muxing of the "data" portion results in a unique
>> identifier that can be mapped to exactly one interrupt handler.
> 
> True, on sparc64 PCI-E controllers, for example, the MSI vector is
> received by the PCI-E host controller, and the host controller turns
> this into a cpu format interrupt packet for the system bus.

Err .. why would a PCIe controller be CPU specific ? Looking at Figure
1-6 of the spec, i think it should be CPU independent ?

Excuse me for my ignorance, just that my head has begun to reel after
reading through PCIe 1.0 and the device specs, still being inconclusive
how to proceed.

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