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Subject: Re: [PATCH 3/6] pinctrl: sunxi: Support the 2.5V I/O bias mode
To:     =?UTF-8?Q?Jernej_=c5=a0krabec?= <jernej.skrabec@gmail.com>,
        Chen-Yu Tsai <wens@csie.org>,
        Linus Walleij <linus.walleij@linaro.org>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Maxime Ripard <mripard@kernel.org>, Ondrej Jirman <x@xff.cz>,
        Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev
References: <20220626021148.56740-1-samuel@sholland.org>
 <20220626021148.56740-4-samuel@sholland.org>
 <1818958.tdWV9SEqCh@jernej-laptop>
From:   Samuel Holland <samuel@sholland.org>
Message-ID: <b1aaa895-59dd-bbb1-3dc1-9dfaa96dfdb0@sholland.org>
Date:   Mon, 27 Jun 2022 22:29:51 -0500
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On 6/27/22 3:43 PM, Jernej Škrabec wrote:
> Dne nedelja, 26. junij 2022 ob 04:11:44 CEST je Samuel Holland napisal(a):
>> H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the
>> 1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level
>> and disabling the "withstand function".
>>
>> H616 supports this capability on its main PIO only. A100 supports this
>> capability on both its PIO and R-PIO.
>>
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>>  drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c |  1 +
>>  drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c   |  2 +-
>>  drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c   |  2 +-
>>  drivers/pinctrl/sunxi/pinctrl-sunxi.c         | 10 ++++++++++
>>  drivers/pinctrl/sunxi/pinctrl-sunxi.h         |  7 +++++++
>>  5 files changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
>> b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c index
>> 21054fcacd34..afc1f5df7545 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
>> @@ -82,6 +82,7 @@ static const struct sunxi_pinctrl_desc a100_r_pinctrl_data
>> = { .npins = ARRAY_SIZE(a100_r_pins),
>>  	.pin_base = PL_BASE,
>>  	.irq_banks = 1,
>> +	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
>>  };
>>
>>  static int a100_r_pinctrl_probe(struct platform_device *pdev)
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
>> b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c index
>> e69f6da40dc0..f682e0e4244d 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
>> @@ -684,7 +684,7 @@ static const struct sunxi_pinctrl_desc a100_pinctrl_data
>> = { .npins = ARRAY_SIZE(a100_pins),
>>  	.irq_banks = 7,
>>  	.irq_bank_map = a100_irq_bank_map,
>> -	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
>> +	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
>>  };
>>
>>  static int a100_pinctrl_probe(struct platform_device *pdev)
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
>> b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c index
>> 152b71226a80..d6ca720ee8d8 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
>> @@ -525,7 +525,7 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_data
>> = { .irq_banks = ARRAY_SIZE(h616_irq_bank_map),
>>  	.irq_bank_map = h616_irq_bank_map,
>>  	.irq_read_needs_mux = true,
>> -	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
>> +	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
>>  };
>>
>>  static int h616_pinctrl_probe(struct platform_device *pdev)
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 3c5e71359ca8..eb3d595f816a
>> 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> @@ -662,6 +662,16 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct
>> sunxi_pinctrl *pctl, reg &= ~IO_BIAS_MASK;
>>  		writel(reg | val, pctl->membase + 
> sunxi_grp_config_reg(pin));
>>  		return 0;
>> +	case BIAS_VOLTAGE_PIO_POW_MODE_CTL:
>> +		val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;
>> +
>> +		raw_spin_lock_irqsave(&pctl->lock, flags);
>> +		reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
>> +		reg &= ~BIT(bank);
>> +		writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
>> +		raw_spin_unlock_irqrestore(&pctl->lock, flags);
>> +
>> +		fallthrough;
> 
> Would this set bit 12 as needed? According to documentation, it's a bit 
> special case, since it covers VCC-IO, port F and port H, at least according to 
> documentation. I guess BIAS_VOLTAGE_PIO_POW_MODE_SEL has same issue.

Right, it seems we would need some mask to tell us which ports are affected by
bit 12, and which have their own setting. The current code is unlikely to cause
any issue, though, because in practice VCC-IO is always 3.3 V.

Regards,
Samuel