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References: <20220627051257.38543-1-samuel@sholland.org> <20220627051257.38543-2-samuel@sholland.org>
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From:   Guo Ren <guoren@kernel.org>
Date:   Tue, 28 Jun 2022 15:55:20 +0800
Message-ID: <CAJF2gTTuBagHb0SHZqFjUP9bryVs=AnOTF8z2pxqEfmX4g14zQ@mail.gmail.com>
Subject: Re: [PATCH v1 1/3] dt-bindings: interrupt-controller: Require trigger
 type for T-HEAD PLIC
To:     Samuel Holland <samuel@sholland.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Prabhakar <prabhakar.csengg@gmail.com>,
        Marc Zyngier <maz@kernel.org>,
        Sagar Kadam <sagar.kadam@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        linux-renesas-soc@vger.kernel.org,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Thomas Gleixner <tglx@linutronix.de>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>
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Reviewed-by: Guo Ren <guoren@kernel.org>

On Mon, Jun 27, 2022 at 1:13 PM Samuel Holland <samuel@sholland.org> wrote:
>
> The RISC-V PLIC specification unfortunately allows PLIC implementations
> to ignore edges seen while an edge-triggered interrupt is being handled:
>
>   Depending on the design of the device and the interrupt handler,
>   in between sending an interrupt request and receiving notice of its
>   handler=E2=80=99s completion, the gateway might either ignore additiona=
l
>   matching edges or increment a counter of pending interrupts.
>
> For PLICs with that misfeature, software needs to know the trigger type
> of each interrupt. This allows it to work around the issue by completing
> edge-triggered interrupts before handling them. Such a workaround is
> required to avoid missing any edges.
>
> The T-HEAD C9xx PLIC is an example of a PLIC with this behavior.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>
>  .../sifive,plic-1.0.0.yaml                    | 31 ++++++++++++++++---
>  1 file changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifiv=
e,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/=
sifive,plic-1.0.0.yaml
> index 27092c6a86c4..3c589cbca851 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-=
1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-=
1.0.0.yaml
> @@ -26,9 +26,13 @@ description:
>    with priority below this threshold will not cause the PLIC to raise it=
s
>    interrupt line leading to the context.
>
> -  While the PLIC supports both edge-triggered and level-triggered interr=
upts,
> -  interrupt handlers are oblivious to this distinction and therefore it =
is not
> -  specified in the PLIC device-tree binding.
> +  The PLIC supports both edge-triggered and level-triggered interrupts. =
For
> +  edge-triggered interrupts, the RISC-V PLIC spec allows two responses t=
o edges
> +  seen while an interrupt handler is active; the PLIC may either queue t=
hem or
> +  ignore them. In the first case, handlers are oblivious to the trigger =
type, so
> +  it is not included in the interrupt specifier. In the second case, sof=
tware
> +  needs to know the trigger type, so it can reorder the interrupt flow t=
o avoid
> +  missing interrupts.
>
>    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
>    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC th=
at
> @@ -65,7 +69,8 @@ properties:
>      const: 0
>
>    '#interrupt-cells':
> -    const: 1
> +    minimum: 1
> +    maximum: 2
>
>    interrupt-controller: true
>
> @@ -91,6 +96,24 @@ required:
>    - interrupts-extended
>    - riscv,ndev
>
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - thead,c900-plic
> +
> +    then:
> +      properties:
> +        '#interrupt-cells':
> +          const: 2
> +
> +    else:
> +      properties:
> +        '#interrupt-cells':
> +          const: 1
> +
>  additionalProperties: false
>
>  examples:
> --
> 2.35.1
>


--=20
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/