Message-ID: <465A6742.4090903@zytor.com>
Date: Sun, 27 May 2007 22:23:14 -0700
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Grant Grundler <grundler@parisc-linux.org>
CC: Roland Dreier <rdreier@cisco.com>, David Miller <davem@davemloft.net>,
       abraham.manu@gmail.com, greg@kroah.com,
       linux-pci@atrey.karlin.mff.cuni.cz, linux-kernel@vger.kernel.org
Subject: Re: PCIE
References: <46561287.8020103@gmail.com> <ada1wh560u1.fsf@cisco.com> <46584C30.4030206@gmail.com> <20070526.154910.78725926.davem@davemloft.net> <ada3b1h3gke.fsf@cisco.com> <20070528041802.GB711@colo.lackof.org>
In-Reply-To: <20070528041802.GB711@colo.lackof.org>
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Grant Grundler wrote:
> On Sun, May 27, 2007 at 06:03:29PM -0700, Roland Dreier wrote:
> ...
>>  > I can imagine many systems where the cpu simply doesn't have enough
>>  > interrupt pins to uniquely identify every possible MSI interrupt
>>  > source.
>>
>> I have a hard time imagining a PCI host bus controller that converts
>> MSI interrupts back to wire interrupts that go to pins on the CPU.
>> For one thing it would be hard to maintain the guarantee that
>> MSI interrupts can't pass DMAs.
> 
> Whatever converts the MSI back to CPU IRQ pins would have to participate
> in the "cache coherency domain". This would avoid issues around DMA ordering.
> It _could_ be on the same silicon as the PCI Host bus controller as long
> as the above is true.
> 

Also, don't forget that a lot of platforms provide *no* hardware cache
coherency.

	-hpa
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