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To:     <michael@walle.cc>, <robh+dt@kernel.org>, <krzk+dt@kernel.org>,
        <Nicolas.Ferre@microchip.com>
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Subject: RE: [PATCH] ARM: dts: lan966x: fix sys_clk frequency
Thread-Topic: [PATCH] ARM: dts: lan966x: fix sys_clk frequency
Thread-Index: AQHYQUllEhXoxvVKzUCVMtm162QkMq1m1zwQ
Date:   Wed, 29 Jun 2022 11:40:14 +0000
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> The sys_clk frequency is 165.625MHz. The register reference of the
> Generic Clock controller lists the CPU clock as 600MHz, the DDR clock as
> 300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
> noticed during the fan driver development and it was measured and
> verified via the CLK_MON output of the SoC which can be configured to
> output sys_clk/64.
>=20
> The core PLL settings (which drives the SYS clock) seems to be as
> follows:
>   DIVF =3D 52
>   DIVQ =3D 3
>   DIVR =3D 1
>=20
> With a refernce clock of 25MHz, this means we have a post divider clock
>   Fpfd =3D Fref / (DIVR + 1) =3D 25MHz / (1 + 1) =3D 12.5MHz
>=20
> The resulting VCO frequency is then
>   Fvco =3D Fpfd * (DIVF + 1) * 2 =3D 12.5MHz * (52 + 1) * 2 =3D 1325MHz
>=20
> And the output frequency is
>   Fout =3D Fvco / 2^DIVQ =3D 1325MHz / 2^3 =3D 165.625Mhz
>=20
> This all adds up to the constrains of the PLL:
>     10MHz <=3D Fpfd <=3D 200MHz
>     20MHz <=3D Fout <=3D 1000MHz
>   1000MHz <=3D Fvco <=3D 2000MHz
>=20
> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board
> pcb8291")
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>

> ---
>  arch/arm/boot/dts/lan966x.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/arch/arm/boot/dts/lan966x.dtsi
> b/arch/arm/boot/dts/lan966x.dtsi
> index 14c9cb3c0f3b..03045ec4aca4 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -38,7 +38,7 @@ clocks {
>                 sys_clk: sys_clk {
>                         compatible =3D "fixed-clock";
>                         #clock-cells =3D <0>;
> -                       clock-frequency =3D <162500000>;
> +                       clock-frequency =3D <165625000>;
>                 };
>=20
>                 cpu_clk: cpu_clk {
> --
> 2.30.2