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From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
        miquel.raynal@bootlin.com, nagasure@xilinx.com, vigneshr@ti.com
Cc:     boris.brezillon@collabora.com, linux-mtd@lists.infradead.org,
        linux-kernel@vger.kernel.org, git@amd.com, richard@nod.at,
        amit.kumar-mahapatra@amd.com, Olga Kitaina <okitain@gmail.com>,
        stable@vger.kernel.org
Subject: Re: [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR
Date:   Wed, 29 Jun 2022 13:38:55 +0200
Message-Id: <20220629113855.283760-1-miquel.raynal@bootlin.com>
In-Reply-To: <20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com>
References: 
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On Tue, 2022-06-28 at 15:48:24 UTC, Amit Kumar Mahapatra wrote:
> From: Olga Kitaina <okitain@gmail.com>
> 
> According to the Arasan NAND controller spec, the flash clock rate for SDR
> must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
> CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
> which would result in incorrect behavior for NV-DDR modes 0-4.
> 
> The appropriate clock rate can be calculated from the NV-DDR timing
> parameters as 1/tCK, or for rates measured in picoseconds,
> 10^12 / nand_nvddr_timings->tCK_min.
> 
> Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
> CC: stable@vger.kernel.org # 5.8+
> Signed-off-by: Olga Kitaina <okitain@gmail.com>
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel