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Date:   Wed, 29 Jun 2022 15:13:46 +0200
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Subject: Re: [PATCH 12/12] i2c: xiic: Correct the BNB interrupt enable
 sequence
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To:     Manikanta Guntupalli <manikanta.guntupalli@xilinx.com>,
        michal.simek@xilinx.com, michal.simek@amd.com,
        linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org,
        linux-kernel@vger.kernel.org, git@amd.com
Cc:     Srinivas Goud <srinivas.goud@xilinx.com>
References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com>
 <1656072327-13628-13-git-send-email-manikanta.guntupalli@xilinx.com>
From:   Krzysztof Adamski <krzysztof.adamski@nokia.com>
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W dniu 24.06.2022 o 14:05, Manikanta Guntupalli pisze:
> From: Srinivas Goud <srinivas.goud@xilinx.com>
>
> With updated AXI IIC IP core(v2.1)there is change in IP behavior
> in dynamic mode, where controller initiate read transfer on IIC
> bus only after getting the value for the number of bytes to receive.
>
> In the existing xiic_start_recv function Bus Not Busy(BNB)
> interrupt is enabled just after "slave address + start"
> write to FIFO and before the "count + stop"write to FIFO.
> Since IIC controller drives the start address of a transaction
> on the bus only after it has received the byte count information
> the above sequence can lead to spurious BNB interrupt in case
> there is any delay after "slave address + start" write to FIFO.
>
> This is fixed by ensuring that BNB interrupt is enabled only
> after "count + stop" has been written to FIFO.
>
> Signed-off-by: Srinivas Goud <srinivas.goud@xilinx.com>
> Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@xilinx.com>
> ---

[...]

Does this spurious interrupt cause any trouble or it is just ignored and 
the only problem is unneeded extra CPU load?

Krzysztof