Received: by 2002:a6b:fb09:0:0:0:0:0 with SMTP id h9csp610156iog; Wed, 29 Jun 2022 06:52:13 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vJSODycyyBIs57IuZBGn24iCXL0vmkzshyInB2JJPvYirpdtiRaKZhC8YzTZcPaK9AvRWo X-Received: by 2002:a05:6402:27c6:b0:435:d24a:d061 with SMTP id c6-20020a05640227c600b00435d24ad061mr4431241ede.427.1656510732945; Wed, 29 Jun 2022 06:52:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656510732; cv=none; d=google.com; s=arc-20160816; b=x3VKgSXCtRta+BQ2gXpWolAmFahodG+0UKt5ZIfIR1yDusI7zxRwAdv9B97aNJ5O+L wJfDaYr8G90kNUDggqTvz81/N9ONAdrF2EYm7DRzZi8rLvxy1x14c5IOrYg5HvfKCwzs vin+6j/jqh+hZN1H97wCbS1vPGlt2nUXcobX5+eycxFC8g8/Q7h3J073yU4IvcXUmLmJ 6kbi9Ki1giLnGarIO/QTIscejIw9fzgwKJhDmb4rUYc+qOWVjkZ+nZqPiTxiE2tHe7pX jrA7NPp5n9j/5E2vI9dwogBRh1y1MZpTb1YoTxopBSAJViuwHsHaIEYiH2vfd1H1vhSP b7Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:subject:cc:to:from:message-id :date:dkim-signature; bh=8R6fgWkyz9eINj8/Xmj9mzedbr/wUgBOxu5rHVNLNKM=; b=E94nSv+Ptq+Cxe5Z+731rshIWeRYjAZqaXgB2RkqO0gqWsjQX/bngSgMVK5nn5srdn lxVDayXcWA31FpGMrGfCShgiqqOn9iienZYTw+NWgvocRN3mktveFywB6pNSWiYsjt8l tpDupqr8I6OaruO1PJpmauuSINIzPCmZEE0syJfVQFxdNwNkB4/OolWpVQS37lafNov+ 2wwKEz5LWtjh+7KwmuEkmcCCHh5Qdnv5UjAhKV867AXzVSrF+FKui9qMPE6fDbwW3yzj IDbdmkvE0/mq8nJHlmXmRh+byX+aPStodJR8Em6Xi5iUaxfkPjJbufn0B/A7hCqEqap7 YsHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=M1hM7y2U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ht16-20020a170907609000b007080395ddefsi19648995ejc.495.2022.06.29.06.51.46; Wed, 29 Jun 2022 06:52:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=M1hM7y2U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233780AbiF2NPK (ORCPT + 99 others); Wed, 29 Jun 2022 09:15:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232215AbiF2NPH (ORCPT ); Wed, 29 Jun 2022 09:15:07 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B43B26AD3 for ; Wed, 29 Jun 2022 06:15:06 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 46D9EB821C3 for ; Wed, 29 Jun 2022 13:15:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D5007C34114; Wed, 29 Jun 2022 13:15:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656508504; bh=KpEJT2MHZoldI60YEXL57k+yjrAEriOyk2skitURIqI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=M1hM7y2UvSWKhwqTYGHLbeVldBdD55Xqn1L3f49w1ndffxEWWld7cRDJstHbM8jLG F9/bMYFfQyDlRFxCJ4ZwZXotrFTigXXjuvIij9Ejb9qiW5GicT8i0sGtk+YgBuRF5c Hc3gKENWid9riLaHUyjXmiboGxyDYbJhLZhdmQ/tSYaZYXN+2Bl9WcIhwLZ0GQ3o/e GirJ6U20jknrs94VfcTLMb8L9WV1lWQam3UtxOjmXgbAULv+eDurzYhlqlUU5rAnsa /SgFhl+Z2Kb5QqXEbLRxBw+dLZP/8dCQ96eITf7NAt6SMzx7iNw8xExHI6A9n1RsUY smZUR058JA2gw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o6XX3-0044hF-Os; Wed, 29 Jun 2022 14:15:01 +0100 Date: Wed, 29 Jun 2022 14:15:01 +0100 Message-ID: <87sfnn1ui2.wl-maz@kernel.org> From: Marc Zyngier To: Jianmin Lv Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: Re: [PATCH V13 07/13] irqchip/loongson-pch-msi: Add ACPI init support In-Reply-To: <1656329997-20524-8-git-send-email-lvjianmin@loongson.cn> References: <1656329997-20524-1-git-send-email-lvjianmin@loongson.cn> <1656329997-20524-8-git-send-email-lvjianmin@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lvjianmin@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, guohanjun@huawei.com, lorenzo.pieralisi@arm.com, jiaxun.yang@flygoat.com, chenhuacai@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 27 Jun 2022 12:39:51 +0100, Jianmin Lv wrote: >=20 > From: Huacai Chen >=20 > We are preparing to add new Loongson (based on LoongArch, not compatible > with old MIPS-based Loongson) support. LoongArch use ACPI other than DT > as its boot protocol, so add ACPI init support. Same rant about the content-less paragraph, which I asked you to drop a few version ago. >=20 > PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in > Section 5 of "Loongson 7A1000 Bridge User Manual". For more information > please refer Documentation/loongarch/irq-chip-model.rst. >=20 > For systems with two chipsets, there are two related msi irqdomains, > each of which has the same node id as its parent irqdomain. So we > use a structure to mantain the relation of node and it's parent > irqdomain as pch irqdomin, and add a pci_segment field to it for > matching the pci segment of a pci device when setting msi irqdomain > for the device. >=20 > struct acpi_vector_group { > int node; > int pci_segment; > struct irq_domain *parent; > }; >=20 > The field 'pci_segment' and 'node' are initialized from MCFG, and > the parent irqdomain will set field 'parent' by matching same > 'node'. >=20 > Co-developed-by: Jianmin Lv > Signed-off-by: Jianmin Lv > Signed-off-by: Huacai Chen > --- > arch/loongarch/include/asm/irq.h | 7 +- > arch/loongarch/kernel/irq.c | 30 ++++++- > drivers/irqchip/irq-loongson-pch-msi.c | 147 +++++++++++++++++++++++----= ------ > 3 files changed, 138 insertions(+), 46 deletions(-) >=20 > diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/as= m/irq.h > index a444dc6..367aa44 100644 > --- a/arch/loongarch/include/asm/irq.h > +++ b/arch/loongarch/include/asm/irq.h > @@ -50,9 +50,11 @@ static inline bool on_irq_stack(int cpu, unsigned long= sp) > =20 > struct acpi_vector_group { > int node; > + int pci_segment; > struct irq_domain *parent; > }; > extern struct acpi_vector_group pch_group[MAX_IO_PICS]; > +extern struct acpi_vector_group msi_group[MAX_IO_PICS]; > =20 > #define CORES_PER_EIO_NODE 4 > =20 > @@ -112,9 +114,8 @@ struct irq_domain *htvec_acpi_init(struct irq_domain = *parent, > struct acpi_madt_ht_pic *acpi_htvec); > int pch_lpc_acpi_init(struct irq_domain *parent, > struct acpi_madt_lpc_pic *acpi_pchlpc); > -struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent, > - struct acpi_madt_msi_pic *acpi_pchmsi); > int find_pch_pic(u32 gsi); > +struct fwnode_handle *get_pch_msi_handle(int pci_segment); > =20 > extern struct acpi_madt_lio_pic *acpi_liointc; > extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS]; > @@ -127,7 +128,7 @@ struct irq_domain *pch_msi_acpi_init(struct irq_domai= n *parent, > extern struct irq_domain *cpu_domain; > extern struct irq_domain *liointc_domain; > extern struct fwnode_handle *pch_lpc_handle; > -extern struct irq_domain *pch_msi_domain[MAX_IO_PICS]; > +extern struct fwnode_handle *pch_msi_handle[MAX_IO_PICS]; > extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS]; > =20 > extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev); > diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c > index f2115be..82bc6c7 100644 > --- a/arch/loongarch/kernel/irq.c > +++ b/arch/loongarch/kernel/irq.c > @@ -27,8 +27,8 @@ > =20 > struct irq_domain *cpu_domain; > struct irq_domain *liointc_domain; > -struct irq_domain *pch_msi_domain[MAX_IO_PICS]; > struct acpi_vector_group pch_group[MAX_IO_PICS]; > +struct acpi_vector_group msi_group[MAX_IO_PICS]; > =20 > /* > * 'what should we do if we get a hw irq event on an illegal vector'. > @@ -55,6 +55,33 @@ int arch_show_interrupts(struct seq_file *p, int prec) > return 0; > } > =20 > +static int early_pci_mcfg_parse(struct acpi_table_header *header) Shouldn't this be __init as well? > +{ > + struct acpi_table_mcfg *mcfg; > + struct acpi_mcfg_allocation *mptr; > + int i, n; > + > + if (header->length < sizeof(struct acpi_table_mcfg)) > + return -EINVAL; > + > + n =3D (header->length - sizeof(struct acpi_table_mcfg)) / > + sizeof(struct acpi_mcfg_allocation); > + mcfg =3D (struct acpi_table_mcfg *)header; > + mptr =3D (struct acpi_mcfg_allocation *) &mcfg[1]; > + > + for (i =3D 0; i < n; i++, mptr++) { > + msi_group[i].pci_segment =3D mptr->pci_segment; > + msi_group[i].node =3D (mptr->address >> 44) & 0xf; > + } > + > + return 0; > +} > + > +void __init init_msi_parent_group(void) > +{ > + acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse); > +} > + > void __init init_IRQ(void) > { > int i; > @@ -68,6 +95,7 @@ void __init init_IRQ(void) > clear_csr_ecfg(ECFG0_IM); > clear_csr_estat(ESTATF_IP); > =20 > + init_msi_parent_group(); The changes in this file should be a separate patch, as it is completely independent. > irqchip_init(); > #ifdef CONFIG_SMP > ipi_irq =3D EXCCODE_IPI - EXCCODE_INT_START; > diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq= -loongson-pch-msi.c > index e3801c4..5db4a68 100644 > --- a/drivers/irqchip/irq-loongson-pch-msi.c > +++ b/drivers/irqchip/irq-loongson-pch-msi.c > @@ -15,14 +15,30 @@ > #include > #include > =20 > +static int nr_pics; > + > struct pch_msi_data { > struct mutex msi_map_lock; > phys_addr_t doorbell; > u32 irq_first; /* The vector number that MSIs starts */ > u32 num_irqs; /* The number of vectors for MSIs */ > unsigned long *msi_map; > + struct fwnode_handle *domain_handle; > }; > =20 > +static struct pch_msi_data *pch_msi_priv[2]; What is this '2'? > + > +struct fwnode_handle *get_pch_msi_handle(int pci_segment) > +{ > + int i; > + > + for (i =3D 0; i < MAX_IO_PICS; i++) { > + if (msi_group[i].pci_segment =3D=3D pci_segment) AFAICT, this driver is supposed to compile on MIPS too. Clearly, you haven't bothered checking that it was still building: drivers/irqchip/irq-loongson-pch-msi.c: In function =E2=80=98get_pch_msi_ha= ndle=E2=80=99: drivers/irqchip/irq-loongson-pch-msi.c:35:18: error: =E2=80=98MAX_IO_PICS= =E2=80=99 undeclared (first use in this function) 35 | for (i =3D 0; i < MAX_IO_PICS; i++) { | ^~~~~~~~~~~ drivers/irqchip/irq-loongson-pch-msi.c:35:18: note: each undeclared identif= ier is reported only once for each function it appears in drivers/irqchip/irq-loongson-pch-msi.c:36:7: error: =E2=80=98msi_group=E2= =80=99 undeclared (first use in this function); did you mean =E2=80=98task_= group=E2=80=99? 36 | if (msi_group[i].pci_segment =3D=3D pci_segment) | ^~~~~~~~~ | task_group I've stopped here. M. --=20 Without deviation from the norm, progress is not possible.