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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id p23-20020a1709061b5700b0070e3f58ed5csm8008044ejg.48.2022.06.29.10.53.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jun 2022 10:53:53 -0700 (PDT) Message-ID: Date: Wed, 29 Jun 2022 19:53:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v6 02/14] dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file Content-Language: en-US To: "Viorel Suman (OSS)" , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Dmitry Torokhov , Srinivas Kandagatla , Dong Aisheng , Fabio Estevam , Shawn Guo , Stefan Agner , Pengutronix Kernel Team , Linus Walleij , Alessandro Zummo , Alexandre Belloni , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui , Wim Van Sebroeck , Guenter Roeck , Sascha Hauer , NXP Linux Team , Abel Vesa , Viorel Suman , Oliver Graute , Liu Ying , Mirela Rabulea , Peng Fan , Ming Qian , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-input@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-pm@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220629164414.301813-1-viorel.suman@oss.nxp.com> <20220629164414.301813-3-viorel.suman@oss.nxp.com> From: Krzysztof Kozlowski In-Reply-To: <20220629164414.301813-3-viorel.suman@oss.nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/06/2022 18:44, Viorel Suman (OSS) wrote: > From: Abel Vesa > > In order to replace the fsl,scu txt file from bindings/arm/freescale, > we need to split it between the right subsystems. This patch documents > separately the 'iomux/pinctrl' child node of the SCU main node. > > Signed-off-by: Abel Vesa > Signed-off-by: Viorel Suman > --- > .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 68 +++++++++++++++++++ > 1 file changed, 68 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > new file mode 100644 > index 000000000000..76a2e7b28172 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml > @@ -0,0 +1,68 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: i.MX SCU Client Device Node - Pinctrl bindings based on SCU Message Protocol > + > +maintainers: > + - Dong Aisheng > + > +description: i.MX SCU Client Device Node > + Client nodes are maintained as children of the relevant IMX-SCU device node. > + This binding uses the i.MX common pinctrl binding. > + (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt) > + > +allOf: > + - $ref: "pinctrl.yaml#" Don't mix the quotes. You changed them to ', so stick with it. > + > +properties: > + compatible: > + enum: > + - fsl,imx8qm-iomuxc > + - fsl,imx8qxp-iomuxc > + - fsl,imx8dxl-iomuxc > + > +patternProperties: > + 'grp$': > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + > + properties: > + fsl,pins: > + description: > + each entry consists of 3 integers and represents the pin ID, the mux value > + and config setting for the pin. The first 2 integers - pin_id and mux_val - are > + specified using a PIN_FUNC_ID macro, which can be found in > + . The last integer CONFIG is > + the pad setting value like pull-up on this pin. Please refer to the > + appropriate i.MX8 Reference Manual for detailed CONFIG settings. > + $ref: /schemas/types.yaml#/definitions/uint32-matrix Look at fsl,imx8mq-pinctrl.yaml. Each item is described (items under items). > + > + required: > + - fsl,pins > + > + additionalProperties: false > + > +required: > + - compatible > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + pinctrl { > + compatible = "fsl,imx8qxp-iomuxc"; > + > + pinctrl_lpuart0: lpuart0grp { > + fsl,pins = < > + 111 0 0x06000020 > + 112 0 0x06000020 > + >; > + }; > + }; Best regards, Krzysztof